公开(公告)号：US5710550A

公开(公告)日：1998-01-20

申请号：US516322

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe

IPC分类号： G06F15/173 ,  H04Q11/04 ,  H03K17/0412

CPC分类号： G06F15/17375 ,  H04Q11/0478

摘要： A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data. The FPID further includes a memory controller for receiving each command from the host controller and for writing data included in the command into each memory cell of a particular subset of the first and second memory cells upon receipt of the command. The address included in the command indicates the particular subset into which the controller is to write the data. The number of memory cells included in the particular subset is a variable function of the address.

摘要翻译： 现场可编程互连设备（FPID）响应于来自主机控制器的命令，有选择地在信号端口之间路由信号。 每个命令包括地址和数据。 FPID包括开关单元阵列，每个开关单元互连一个单独的端口对，并且每个具有第一和第二控制信号输入。 当第一和第二控制信号均被断言时，开关单元在其互连的一对端口之间提供信号路径。 FPID包括用于存储数据的第一和第二组存储器单元。 每个第一存储器单元对应于开关单元中的单独单元，并根据其存储的数据选择性地断言或解除输入到相应开关单元的第一控制信号。 每个第二存储器单元对应于单独的开关单元组，并根据其存储的数据选择性地断言或解除输入到相应组的每个开关单元的第二控制信号。 FPID还包括存储器控制器，用于从主机控制器接收每个命令，并且用于在接收到命令时将包括在命令中的数据写入第一和第二存储器单元的特定子集的每个存储单元。 命令中包含的地址表示控制器写入数据的特定子集。 包含在特定子集中的存储单元的数量是地址的可变函数。

公开(公告)号：US5734334A

公开(公告)日：1998-03-31

申请号：US516320

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： H03K19/173 ,  H04Q1/00

CPC分类号： H03K19/1736

摘要： An electronic crossbar switch employs a switch array for selectively routing digital and analog signals between its terminals. A separate port for each terminal provides a path for digital and analog signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal with or without an input direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal.

摘要翻译： 电子交叉开关采用开关阵列，用于在其端子之间选择性地路由数字和模拟信号。 每个端子的独立端口为数字和模拟信号流入和流出交换机提供了路径。 每个端口可被配置为在三态控制信号的控制下具有或不具有三态缓冲器，以响应于时钟和时钟使能信号来选择性地锁存输入或输出信号，以及缓冲通过或者流过开关端子的信号， 没有输入方向控制信号。 为所有端口提供一组控制输入，允许外部主机与每个端口并行发送控制信号。 每个端口可以被编程为选择其任何控制输入作为其三态，时钟使能，时钟或方向控制信号。

公开(公告)号：US5717871A

公开(公告)日：1998-02-10

申请号：US516319

申请日：1995-08-17

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： G06F13/40 ,  H04L12/56 ,  H04Q3/68 ,  G06F3/00

CPC分类号： G06F13/4022 ,  H04L49/25 ,  H04Q3/68 ,  H04L49/254 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/3027 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13106 ,  H04Q2213/13141 ,  H04Q2213/13214 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： An electronic crossbar switch employs a switch array for selectively routing signals between its terminals. A separate port provided for each terminal buffers signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal in response to a direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal. A parallel "key" bus is also provided in common to all ports for conveying a key address from the host controller. Each port stores an internal port address and when the key address matches the port address, the port asserts an internal "KEY" signal. Each port may be configured to use the KEY signal selectively as either its tristate, clock enable, clock or direction control signal.

摘要翻译： 电子交叉开关采用开关阵列，用于在其端子之间选择性地路由信号。 为每个端子提供的单独端口缓冲流入和流出开关的信号。 每个端口可以被配置为在三态控制信号的控制下操作有或没有三态缓冲，以响应于时钟和时钟使能信号来选择性地锁存输入或输出信号，以及响应于缓冲转换到终端的信号 到方向控制信号。 为所有端口提供一组控制输入，允许外部主机与每个端口并行发送控制信号。 每个端口可以被编程为选择其任何控制输入作为其三态，时钟使能，时钟或方向控制信号。 还向所有端口提供并行“键”总线，用于从主机控制器传送密钥地址。 每个端口存储内部端口地址，当密钥地址与端口地址匹配时，端口置位一个内部“KEY”信号。 每个端口可以被配置为选择性地使用KEY信号作为其三态，时钟使能，时钟或方向控制信号。

公开(公告)号：US5790048A

公开(公告)日：1998-08-04

申请号：US961545

申请日：1997-10-30

申请人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

发明人： Wen-Jai Hsieh ,  Chi-Song Horng ,  Chun Chiu Daniel Wong ,  Gerchih Chou ,  Shrikant Sathe ,  Kent Dahlgren

IPC分类号： H03K19/173 ,  H04Q1/00 ,  G06F13/00

CPC分类号： H03K19/1736

摘要： A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.

摘要翻译： 交叉点交换机通过从主机控制器的路由数据定义的路由模式在其终端之间路由信号。 交叉点开关包括传输晶体管阵列。 每个通过晶体管在导通时提供一个信号路径，互连独立的一对开关端子。 交叉点开关还包括两个静态随机存取存储体。 每个存储体存储定义单独路由模式的路由数据，并产生反映其存储的数据的单独的一组输出信号。 多路复用器将所选择的一个存储器组的输出信号传送到开关阵列，以控制其传输晶体管，使得开关阵列实现由所选存储体中的数据定义的布线图案。 通过将定义不同路由模式的路由数据加载到两个存储体中，主控制器随后可以通过切换多路复用器的控制输入来快速地使交叉点开关交替在两个路由模式之间。

公开(公告)号：US08410834B2

公开(公告)日：2013-04-02

申请号：US13044677

申请日：2011-03-10

申请人： Chia-Liang Lin ,  Gerchih Chou ,  Pei-Si Wu

发明人： Chia-Liang Lin ,  Gerchih Chou ,  Pei-Si Wu

IPC分类号： H03L7/00

CPC分类号： H04L7/0079 ,  H04L7/033 ,  H04L7/0337

摘要： An apparatus and method for clock regeneration with low jitter. The method includes the following steps: (a) using a phase lock loop to generate a first clock that is phase locked to a reference clock; (b) using a binary phase detector for generating a phase error signal by detecting a timing difference between the input signal and a second clock; (c) filtering the phase error signal to generate a first control word and a second control word; (d) performing a phase rotation on the first clock by an amount controlled by the first control word to generate the second clock; (e) filtering the second control word to generate a third control word; (f) sampling the third control word to generate a fourth control word using a third clock; and (g) performing a phase rotation on the first clock by an amount controlled by the fourth control word to generate the third clock. Comparable features for performing these steps are provided in the apparatus.

摘要翻译： 一种具有低抖动时钟再生的装置和方法。 该方法包括以下步骤：（a）使用锁相环产生锁相到参考时钟的第一时钟; （b）使用二进制相位检测器，通过检测输入信号和第二时钟之间的定时差产生相位误差信号; （c）对相位误差信号进行滤波以产生第一控制字和第二控制字; （d）在所述第一时钟上执行由所述第一控制字控制的量的相位旋转以产生所述第二时钟; （e）过滤所述第二控制字以产生第三控制字; （f）使用第三时钟对第三控制字进行采样以产生第四控制字; 以及（g）在所述第一时钟上执行由所述第四控制字控制的量的相位旋转以产生所述第三时钟。 在该装置中提供了用于执行这些步骤的相当特征。

公开(公告)号：US07924113B2

公开(公告)日：2011-04-12

申请号：US12349740

申请日：2009-01-07

申请人： Gerchih Chou ,  Chia-Liang Lin

发明人： Gerchih Chou ,  Chia-Liang Lin

IPC分类号： H03H7/38 ,  H04B3/14

CPC分类号： H04B3/14 ,  H01L23/64 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00014 ,  H01L2924/00

摘要： A passive equalizer circuit incorporated at a front-end of an integrated receiver circuit uses passive components that are distributed between inside and outside of an integrated circuit package. The passive equalizer circuit has off-chip components that are placed on a printed circuit board and on-chip components that are fabricated on a common integrated circuit die as a receiver chip. The on-chip components include one or more variable resistors for adjusting a degree of equalization. The off-chip components include one or more resistors for fine tuning input impedance matching of the integrated receiver circuit.

摘要翻译： 集成在集成接收器电路的前端的无源均衡器电路使用分布在集成电路封装的内部和外部的无源部件。 无源均衡器电路具有放置在印刷电路板上的片外部件和在作为接收器芯片的公共集成电路管芯上制造的片上部件。 片上组件包括用于调节均衡程度的一个或多个可变电阻器。 片外部件包括一个或多个用于微调集成接收器电路的输入阻抗匹配的电阻器。

公开(公告)号：US07560991B2

公开(公告)日：2009-07-14

申请号：US11674150

申请日：2007-02-13

申请人： Chia-Liang Lin ,  Gerchih Chou ,  Chao-Cheng Lee

发明人： Chia-Liang Lin ,  Gerchih Chou ,  Chao-Cheng Lee

IPC分类号： H03F1/14

CPC分类号： H03F1/086 ,  H03F1/3211 ,  H03F3/45183 ,  H03F2200/153 ,  H03F2203/45511 ,  H03F2203/45512 ,  H03F2203/45514

摘要： An operational amplifier is dynamically compensated depending on the internal state of the operational amplifier. Compensation is fully enabled only when the internal state indicates a risk of instability. When the internal state of the operational amplifier indicates there is no risk of instability, the compensation is totally or partially turned off.

摘要翻译： 运算放大器根据运算放大器的内部状态进行动态补偿。 仅当内部状态表示不稳定的风险时，补偿才能完全启用。 当运算放大器的内部状态表明不存在不稳定的风险时，补偿完全或部分关闭。

公开(公告)号：US07450041B2

公开(公告)日：2008-11-11

申请号：US11277939

申请日：2006-03-29

申请人： Chia-Liang Lin ,  Gerchih Chou

发明人： Chia-Liang Lin ,  Gerchih Chou

IPC分类号： H03M1/06

CPC分类号： H03F3/005 ,  G11C27/026

摘要： An error canceling comparator based switch capacitor (CBSC) circuit cyclically works through multiple phases including a sampling phase and a transfer phase. During the sampling phase, an input voltage and also an error due to circuit non-idealities are sampled. During the transfer phase, the sampled input voltage is amplified by a fixed ratio and transferred to an output load, while the error is cancelled by reversing the polarity of connection for an internal capacitor within the CBSC circuit.

摘要翻译： 基于误差消除比较器的开关电容器（CBSC）电路通过多个相位循环工作，包括采样相位和转移相位。 在采样阶段，采样输入电压以及电路非理想的误差。 在传送阶段，采样输入电压以固定比率放大并转移到输出负载，而通过反转CBSC电路内部电容器的连接极性来消除误差。

公开(公告)号：US07388407B2

公开(公告)日：2008-06-17

申请号：US11860108

申请日：2007-09-24

申请人： Chia-Liang Lin ,  Gerchih Chou

发明人： Chia-Liang Lin ,  Gerchih Chou

IPC分类号： H03B21/50 ,  H03L7/00

CPC分类号： H03L7/0812 ,  H03L7/0896

摘要： In an embodiment, a fine resolution of variable clock delay is implemented using a variable DC offset having fine resolution. The proportional ratio between the DC offset and the phase delay/advance of the clock is calibrated in a closed-loop manner. In another embodiment, in a calibration circuit, an adaptive positive DC offset is added to the output of a delay buffer to advance the phase of the clock output, which also has a phase delay from the delay buffer. The DC offset is adjusted in a closed-loop manner to make the phase advance, due to the DC offset, compensate for the phase delay, due to the delay buffer. Once the phase relationship of the DC offset to the clock phase advance is calibrated, the DC offset can be scaled and added to the output of another buffer of the same type to achieve a desired phase delay or advance of the clock signal.

摘要翻译： 在一个实施例中，使用具有精细分辨率的可变DC偏移来实现可变时钟延迟的精细分辨率。 DC偏移和时钟的相位延迟/提前之间的比例比例以闭环方式校准。 在另一个实施例中，在校准电路中，自适应正DC偏移被加到延迟缓冲器的输出端，以推进时钟输出的相位，该时钟输出也具有来自延迟缓冲器的相位延迟。 由于延迟缓冲，由于DC偏移补偿相位延迟，DC偏移以闭环方式进行调整，使相位提前。 一旦DC偏移到时钟相位超前的相位关系被校准，则可以将DC偏移量化并相加到相同类型的另一个缓冲器的输出，以实现期望的相位延迟或时钟信号的提前。

公开(公告)号：US20070247201A1

公开(公告)日：2007-10-25

申请号：US11517414

申请日：2006-09-08

申请人： Chia-Liang Lin ,  Gerchih Chou

发明人： Chia-Liang Lin ,  Gerchih Chou

IPC分类号： H03L7/06

CPC分类号： H03L7/07 ,  H03L7/0812 ,  H03L7/0893 ,  H03L7/093

摘要： A delay lock clock synthesizer comprises: an adjustable delay circuit for receiving an input clock and for generating an output clock having a phase offset controlled by a control signal; a phase detector for detecting a phase difference between the input clock and the output clock and for generating a phase error signal representing the phase difference; a summing circuit for summing the phase error signal and a phase offset signal into a modified phase error signal; and a filter for filtering the modified phase error signal to generate the control signal to control the adjustable delay circuit.

摘要翻译： 延迟锁定时钟合成器包括：可调延迟电路，用于接收输入时钟并产生具有由控制信号控制的相位偏移的输出时钟; 相位检测器，用于检测输入时钟和输出时钟之间的相位差，并产生表示相位差的相位误差信号; 求和电路，用于将相位误差信号和相位偏移信号相加到修正的相位误差信号中; 以及用于对修改的相位误差信号进行滤波以产生控制信号以控制可调延迟电路的滤波器。