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    THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF
    1.
    发明申请
    THIN FILM TRANSISTOR DISPLAY PANEL AND MANUFACTURING METHOD THEREOF 有权
    薄膜晶体管显示面板及其制造方法

    公开(公告)号：US20130146864A1

    公开(公告)日：2013-06-13

    申请号：US13464613

    申请日：2012-05-04

    Applicant: Ki-Won KIM ,  Kap Soo YOON ,  Woo Geun LEE ,  Jin-Won LEE ,  Se-Myung KWON ,  Jung Ouck AHN ,  Si Jin KIM

    Inventor： Ki-Won KIM ,  Kap Soo YOON ,  Woo Geun LEE ,  Jin-Won LEE ,  Se-Myung KWON ,  Jung Ouck AHN ,  Si Jin KIM

    IPC: H01L29/786 ,  H01L33/08 ,  H01L21/336

    CPC classification number: H01L29/41733 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/66765 ,  H01L29/78696

    Abstract: A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode.

    Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成从栅极线突出的栅极线和栅电极; 在栅极线和栅电极上形成栅极绝缘层; 在栅极绝缘层上依次沉积半导体材料和金属材料; 使用第一掩模对所述半导体材料和所述金属材料进行第一蚀刻操作以形成半导体层和金属层，所述金属层包括数据线，源电极和漏电极，其中所述漏电极突出 数据线，源电极和漏电极具有整体形状; 以及使用第二掩模对所述金属层进行第二蚀刻操作以分割所述源电极和所述漏电极。

    Thin film transistor display panel and manufacturing method thereof
    4.
    发明授权
    Thin film transistor display panel and manufacturing method thereof 有权
    薄膜晶体管显示面板及其制造方法

    公开(公告)号：US09178024B2

    公开(公告)日：2015-11-03

    申请号：US13464613

    申请日：2012-05-04

    Applicant: Ki-Won Kim ,  Kap Soo Yoon ,  Woo Geun Lee ,  Jin-Won Lee ,  Se-Myung Kwon ,  Jung Ouck Ahn ,  Si Jin Kim

    Inventor： Ki-Won Kim ,  Kap Soo Yoon ,  Woo Geun Lee ,  Jin-Won Lee ,  Se-Myung Kwon ,  Jung Ouck Ahn ,  Si Jin Kim

    IPC: H01L21/00 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786

    CPC classification number: H01L29/41733 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/66765 ,  H01L29/78696

    Abstract: A method for manufacturing a thin film transistor array panel includes forming a gate line and a gate electrode protruding from the gate line on a substrate; forming a gate insulating layer on the gate line and the gate electrode; depositing sequentially a semiconductor material and a metal material on the gate insulating layer; performing a first etching operation on the semiconductor material and the metal material using a first mask to form a semiconductor layer and a metal layer, the metal layer including a data line, a source electrode, and a drain electrode, in which the drain electrode protrudes from the data line, and the source electrode and the drain electrode having an integral shape; and performing a second etching operation on the metal layer using a second mask to divide the source electrode and the drain electrode.

    Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括：在基板上形成从栅极线突出的栅极线和栅电极; 在栅极线和栅电极上形成栅极绝缘层; 在栅极绝缘层上依次沉积半导体材料和金属材料; 使用第一掩模对所述半导体材料和所述金属材料进行第一蚀刻操作以形成半导体层和金属层，所述金属层包括数据线，源电极和漏电极，其中所述漏电极突出 数据线，源电极和漏电极具有整体形状; 以及使用第二掩模对所述金属层进行第二蚀刻操作以分割所述源电极和所述漏电极。

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