公开(公告)号：US20180041212A1

公开(公告)日：2018-02-08

申请号：US15725123

申请日：2017-10-04

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE ,  Yasuhiro AGATA ,  Yoshinobu YAMAGAMI

IPC: H03K19/017 ,  H03K17/12 ,  H03K19/094 ,  H03K19/0952 ,  H01L21/00 ,  H01L29/00

CPC classification number: H03K19/01721 ,  H01L21/00 ,  H01L29/00 ,  H03K17/122 ,  H03K19/094 ,  H03K19/0952

Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

公开(公告)号：US20250063711A1

公开(公告)日：2025-02-20

申请号：US18939347

申请日：2024-11-06

Applicant: Socionext Inc.

Inventor： Yoshinobu YAMAGAMI

IPC: H10B10/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.

公开(公告)号：US20220359541A1

公开(公告)日：2022-11-10

申请号：US17872810

申请日：2022-07-25

Applicant: Socionext Inc.

Inventor： Yoshinobu YAMAGAMI ,  Shinichi MORIWAKI

IPC: H01L27/11

Abstract: Nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.

公开(公告)号：US20210241817A1

公开(公告)日：2021-08-05

申请号：US17211552

申请日：2021-03-24

Applicant: SOCIONEXT INC.

Inventor： Yoshinobu YAMAGAMI

IPC: G11C11/408 ,  G11C11/4094 ,  G11C5/06

Abstract: A memory cell of a 2-port static random access memory (SRAM) includes first and second p-type transistors and first to sixth n-type transistors. Gate interconnects extend in the X direction and are arranged in three rows in the Y direction. The gate interconnects in the first row form gates of the first n-type transistor, the first p-type transistor, and the fourth n-type transistor, the gate interconnect in the second row forms gates of the fifth and sixth n-type transistors, and the gate interconnects in the third row form gates of the third n-type transistor, the second n-type transistor, and the second p-type transistor.

公开(公告)号：US20220108992A1

公开(公告)日：2022-04-07

申请号：US17553675

申请日：2021-12-16

Applicant: SOCIONEXT INC.

Inventor： Yoshinobu YAMAGAMI

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: Static Random Access Memory (SRAM) cell using Complementary FET (CFET) includes the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.

公开(公告)号：US20200051619A1

公开(公告)日：2020-02-13

申请号：US16657895

申请日：2019-10-18

Applicant: SOCIONEXT INC.

Inventor： Yoshinobu YAMAGAMI

IPC: G11C11/419 ,  G11C11/418

Abstract: A semiconductor storage circuit has: a plurality of first memory cells and a first precharge transistor connected to a first local read bit line; and a plurality of second memory cells and a second precharge transistor connected to a second local read bit line. A signal responsive to signals output to the first and second local read bit lines is output to a global read bit line via a gate circuit and an output circuit. A first transistor having a gate connected to the output of the gate circuit is provided between the first and second local read bit lines.

公开(公告)号：US20200005838A1

公开(公告)日：2020-01-02

申请号：US16452365

申请日：2019-06-25

Applicant: SOCIONEXT INC.

Inventor： Yoshinobu YAMAGAMI

IPC: G11C7/12 ,  G11C8/08 ,  G11C5/14 ,  G11C7/10 ,  G11C7/22

Abstract: In a semiconductor memory device, a memory cell array includes a plurality of memory cells. A write circuit includes a negative potential generating circuit that generates a potential lower than a lower power supply potential applied to the memory cells. When a write mask signal indicates an enabled state, the write circuit activates the negative potential generating circuit, and supplies the potential generated by the negative potential generating circuit to a bit line to be supplied with low data. On the other hand, when the write mask signal indicates a disabled state, the write circuit supplies no data to bit line pairs, and inactivates the negative potential generating circuit.

公开(公告)号：US20200350305A1

公开(公告)日：2020-11-05

申请号：US16929913

申请日：2020-07-15

Applicant: SOCIONEXT INC.

Inventor： Yoshinobu YAMAGAMI

IPC: H01L27/02 ,  H01L23/528 ,  H01L27/092 ,  H01L27/11 ,  H01L29/06 ,  H01L29/78

Abstract: Provided is a layout structure capable of reducing the parasitic capacitance between storage nodes of an SRAM cell using vertical nanowire (VNW) FETs. In the SRAM cell, a first storage node is connected to top electrodes of some transistors, and a second storage node is connected to bottom electrodes of other transistors. Accordingly, the first and second storage nodes have fewer regions adjacent to each other in a single layer.

公开(公告)号：US20160211839A1

公开(公告)日：2016-07-21

申请号：US15080406

申请日：2016-03-24

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE ,  Yasuhiro AGATA ,  Yoshinobu YAMAGAMI

IPC: H03K17/16 ,  H01L29/78

CPC classification number: H03K19/01721 ,  H01L21/00 ,  H01L29/00 ,  H03K17/122 ,  H03K19/094 ,  H03K19/0952

Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

Abstract translation: 本文公开了一种驱动器电路，其包括设置在第一和第二节点之间的第一组晶体管，并且包括其中n等于或大于1的晶体管的n个，以及与第一组并联设置的第二组晶体管 的晶体管，其中m为m以上且m为1以上且不等于n的晶体管，m个晶体管串联连接在一起。 第一组中的n沟道晶体管和第二组中的两个n沟道晶体管中的至少一个具有连接到输入节点的栅极。

公开(公告)号：US20160189756A1

公开(公告)日：2016-06-30

申请号：US15064381

申请日：2016-03-08

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE ,  Yoshinobu YAMAGAMI

IPC: G11C7/06 ,  H01L27/105 ,  G11C5/14

CPC classification number: G11C7/062 ,  G11C5/148 ,  G11C7/065 ,  G11C7/12 ,  G11C11/419 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A cross-coupled circuit provided between first and second bit lines that form a bit line pair includes first to fourth fin transistors of p-channel type. The first transistor has its source connected to a first power supply and its gate connected to the second bit line. The second transistor has its source connected to the first power supply and its gate connected to the first bit line. The third transistor has its source connected to the first transistor's drain and its drain connected to the first bit line. The fourth transistor has its source connected to the second transistor's drain and its drain connected to the second bit line.

Abstract translation: 设置在形成位线对的第一和第二位线之间的交叉耦合电路包括p沟道型的第一至第四鳍式晶体管。 第一晶体管的源极连接到第一电源，其栅极连接到第二位线。 第二晶体管的源极连接到第一电源，其栅极连接到第一位线。 第三晶体管的源极连接到第一晶体管的漏极，其漏极连接到第一位线。 第四晶体管的源极连接到第二晶体管的漏极，其漏极连接到第二位线。