公开(公告)号：US20230395604A1

公开(公告)日：2023-12-07

申请号：US18234678

申请日：2023-08-16

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/118 ,  H01L29/06 ,  H01L27/092 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L29/06 ,  H01L27/092 ,  H01L27/0207 ,  H01L21/823871

Abstract: Provided is a semiconductor integrated circuit device including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the device easy. A standard cell having no logical function is disposed adjacent to a standard cell having a logical function. The standard cell includes nanowire FETs having nanowires and pads. The standard cell further includes dummy pads, which have no contribution to a logical function of a circuit.

公开(公告)号：US20200273850A1

公开(公告)日：2020-08-27

申请号：US15931171

申请日：2020-05-13

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/02 ,  H01L29/66 ,  H01L23/528

Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.

公开(公告)号：US20190148380A1

公开(公告)日：2019-05-16

申请号：US16245164

申请日：2019-01-10

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/092 ,  H01L29/66 ,  H01L27/088 ,  H01L27/02 ,  H01L27/06

Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.

公开(公告)号：US20180097004A1

公开(公告)日：2018-04-05

申请号：US15835133

申请日：2017-12-07

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/092 ,  H01L29/66 ,  H01L27/02 ,  H01L27/06 ,  H01L27/088

CPC classification number: H01L27/0924 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0676 ,  H01L27/0886 ,  H01L29/6681

Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.

公开(公告)号：US20170243788A1

公开(公告)日：2017-08-24

申请号：US15590201

申请日：2017-05-09

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L21/82 ,  H01L29/786 ,  H01L27/04 ,  H01L27/092 ,  H01L21/822 ,  H01L21/8238

CPC classification number: H01L21/82 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/0207 ,  H01L27/0255 ,  H01L27/04 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/786 ,  H01L29/78654

Abstract: Disclosed herein is a technique for providing a layout structure for a semiconductor integrated circuit with SOI transistors with an antenna error that could occur in a buried insulator under a source or drain taken into account. A standard cell, which is at least one of a plurality of standard cells that form the semiconductor integrated circuit, includes a signal interconnect serving as an output node to output a signal to outside of the standard cell, and an antenna diode formed between the signal interconnect and a substrate or a

公开(公告)号：US20160204107A1

公开(公告)日：2016-07-14

申请号：US15079987

申请日：2016-03-24

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H03K19/00

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/6681 ,  H03K19/0013

Abstract: Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where m is greater than n, and has its gate connected to a second input node.

Abstract translation: 这里公开了一种驱动器电路，其包括串联连接在第一和第二节点之间的第一和第二n沟道晶体管。 第一n沟道晶体管由具有相同栅极长度和相同栅极宽度的n个鳍状晶体管组成，其中n等于或大于1，并且其栅极连接到第一输入节点。 第二n沟道晶体管由具有相同栅极长度和相同栅极宽度的m个鳍状晶体管组成，其中m大于n，并且其栅极连接到第二输入节点。

公开(公告)号：US20240395944A1

公开(公告)日：2024-11-28

申请号：US18793415

申请日：2024-08-02

Applicant: Socionext Inc.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L27/118 ,  H01L27/12 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US20240021735A1

公开(公告)日：2024-01-18

申请号：US18358689

申请日：2023-07-25

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H01L29/775 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/11807 ,  H01L29/06 ,  H01L29/775 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L21/823412

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire PET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US20210066508A1

公开(公告)日：2021-03-04

申请号：US17095593

申请日：2020-11-11

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L29/786 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/118 ,  H01L29/06 ,  H01L29/775 ,  H01L27/088 ,  H01L29/417 ,  H01L29/423

Abstract: Provided is a semiconductor chip including a nanowire field effect transistor (FET) and having a layout configuration effective for making manufacturing the chip easy. A semiconductor chip includes a first block including a standard cell having a nanowire FET and a second block including a nanowire FET. In the first and second blocks, nanowires extending in an X direction have an arrangement pitch in a Y direction of an integer multiple of a pitch P1. Pads have an arrangement pitch in the X direction of an integer multiple of a pitch P2.

公开(公告)号：US20210013201A1

公开(公告)日：2021-01-14

申请号：US17039051

申请日：2020-09-30

Applicant: SOCIONEXT INC.

Inventor： Hiroyuki SHIMBO

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/118 ,  H01L21/84 ,  H01L27/12 ,  H01L23/528

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.