公开(公告)号：US06601215B1

公开(公告)日：2003-07-29

申请号：US09495554

申请日：2000-02-01

申请人： Stefan Thurnhofer

发明人： Stefan Thurnhofer

IPC分类号： H03M1341

CPC分类号： H03M13/6502 ,  H03M13/4169

摘要： This invention concerns a novel traceback memory management method and apparatus in which a memory stores Viterbi trellis state records and shifts the records in a manner so that the memory mirrors the relevant portion of the trellis accessed during the traceback for error correction and decoding. Several pointers are used so that a random access memory (RAM) can store and access the Viterbi trellis state records with only a minimum amount of hardware required to implement the memory accesses. In certain instances, where memory length is a power of 2, entire elements needed in the address generation steps are eliminated by the invention, thereby saving valuable chip area and clock cycles.

摘要翻译： 本发明涉及一种新颖的回溯存储器管理方法和装置，其中存储器存储维特比网格状态记录并以使得存储器反映在回溯期间访问的网格的相关部分进行纠错和解码的方式移位记录。 使用几个指针，使得随机存取存储器（RAM）可以仅存储实现存储器访问所需的最少量的硬件来存储和访问维特比网格状态记录。 在某些情况下，在存储器长度为2的幂的情况下，通过本发明消除了地址生成步骤中所需的全部元素，从而节省了有价值的芯片面积和时钟周期。

公开(公告)号：US5935266A

公开(公告)日：1999-08-10

申请号：US746727

申请日：1996-11-15

申请人： Stefan Thurnhofer ,  Shaun P. Whalen

发明人： Stefan Thurnhofer ,  Shaun P. Whalen

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G06F11/36 ,  G01R31/28

CPC分类号： G06F11/2236 ,  G01R31/31705 ,  G01R31/318552 ,  G06F11/3656

摘要： A method and apparatus are disclosed for powering-up a microprocessor in a system under debugger control. The microprocessor comprises I/O connection pins, internal logic, and a reset condition responsive to a reset signal. Additionally, the microprocessor has a boundary scan architecture, such as an IEEE 1149.1 (JTAG) compliant interface, which includes a boundary scan register (BSR) and at least one design-specific test data register. The BSR has normal and test modes. In the normal mode, the BSR operatively connects the internal logic to the I/O connection pins. In the test mode, the BSR operatively isolates the internal logic from the I/O connection pins. The method comprising first detecting when power is applied to the microprocessor. Once power is detected and while the microprocessor remains in the reset condition, the BSR is put into tile test mode to isolate the internal logic from the I/O connection pins. Next, the debugger controls the microprocessor via the data register of the JTAG interface, conducting the necessary functions pursuant to power-up. Once the power-up functions are performed and the reset signal is disasserted, the internal logic can be reconnected with the I/O connection pins by returning the BSR to its normal mode.

摘要翻译： 公开了一种用于在调试器控制下在系统中为微处理器供电的方法和装置。 微处理器包括I / O连接引脚，内部逻辑和响应复位信号的复位条件。 此外，微处理器具有边界扫描架构，例如IEEE 1149.1（JTAG）兼容接口，其包括边界扫描寄存器（BSR）和至少一个设计专用测试数据寄存器。 BSR具有正常和测试模式。 在正常模式下，BSR可操作地将内部逻辑连接到I / O连接引脚。 在测试模式下，BSR可以将内部逻辑与I / O连接引脚隔离。 该方法包括首先检测何时向微处理器施加电力。 一旦检测到电源，并且当微处理器保持复位状态时，BSR进入瓦片测试模式，以将内部逻辑与I / O连接引脚隔离。 接下来，调试器通过JTAG接口的数据寄存器控制微处理器，执行上电所需的功能。 一旦执行上电功能并且复位信号被分离，则通过将BSR返回到其正常模式，内部逻辑可以与I / O连接引脚重新连接。

公开(公告)号：US06397240B1

公开(公告)日：2002-05-28

申请号：US09252500

申请日：1999-02-18

申请人： John Susantha Fernando ,  Stefan Thurnhofer

发明人： John Susantha Fernando ,  Stefan Thurnhofer

IPC分类号： G06F700

CPC分类号： G06F7/57 ,  G06F7/523 ,  G06F7/5318 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/325 ,  G06F9/3879 ,  G06F9/3885 ,  G06F17/10 ,  G06F2207/382 ,  G06F2207/3828

摘要： A programmable multi-mode accelerator is disclosed for use with a programmable processor or microprocessor. The programmable multi-mode accelerator allows a programmable processor to execute specific algorithms, such as certain types of finite impulse response (FIR), correlation and Viterbi computations, that require low-precision operations at an extremely high rate. The accelerator extends the digital signal processor's performance into the required range for low-precision computations. The accelerator can be coupled with the main data path of a programmable processor or microprocessor and can directly read and write to the main register files of the programmable processor. In an illustrative implementation, the accelerator data path accesses its input values (source operands) directly from a main register file of the programmable processor and writes results back into a second main register file. The accelerator allows a plurality of low-precision algorithms requiring primarily addition or multiply-add computations, such as finite impulse response, correlation and Viterbi computations, to utilize the same adder cells. The accelerator includes a multi-mode adder that can be programmatically reconfigured to perform various addition computations. In a first mode, referred to as the “single-add mode,” the adder operates as a 17-input 16-bit adder. The single-add mode can be utilized to perform finite impulse response and correlation computations. The second mode, referred to as the “ACS mode,” can be utilized to perform Viterbi computations. The accelerator has a small instruction set and instruction memory and, once started by the main data path, the accelerator executes its own instruction stream. In addition, the accelerator includes a delay line having delays of z−1 or z−2.

摘要翻译： 公开了一种与可编程处理器或微处理器一起使用的可编程多模式加速器。 可编程多模式加速器允许可编程处理器执行诸如某些类型的有限脉冲响应（FIR），相关和维特比计算等特定算法，其需要以非常高的速率进行低精度运算。 加速器将数字信号处理器的性能扩展到低精度计算所需的范围。 加速器可以与可编程处理器或微处理器的主数据通路耦合，并且可以直接读写可编程处理器的主寄存器文件。 在说明性实现中，加速器数据路径直接从可编程处理器的主寄存器文件访问其输入值（源操作数），并将结果写回第二主寄存器文件。 加速器允许需要主要的加法或乘法加法的多个低精度算法，例如有限脉冲响应，相关和维特比计算，以利用相同的加法器单元。 加速器包括可以以编程方式重新配置以执行各种加法运算的多模式加法器。 在称为“单加法”的第一模式中，加法器作为17输入16位加法器操作。 单加法可用于执行有限脉冲响应和相关计算。 被称为“ACS模式”的第二模式可用于执行维特比计算。 加速器具有小的指令集和指令存储器，并且一旦由主数据路径启动，加速器执行其自身的指令流。 此外，加速器包括具有z-1或z-2的延迟的延迟线。

公开(公告)号：US06272616B1

公开(公告)日：2001-08-07

申请号：US09099192

申请日：1998-06-17

申请人： John S. Fernando ,  Stefan Thurnhofer

发明人： John S. Fernando ,  Stefan Thurnhofer

IPC分类号： G06F1500

CPC分类号： G06F9/3828 ,  G06F9/30032 ,  G06F9/30079 ,  G06F9/3009 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： A parallel processing architecture for a digital processor capable of alternately operating in a single threaded mode, a SIMD (single instruction, multiple data) mode and a MIMD (multiple instructions, multiple data) mode. The instruction set for the processor includes instructions for switching between modes and exchanging data between the parallel processing paths. The hardware in any instruction path or portion of an instruction path which is not being used is deactivated to save power.

摘要翻译： 一种能够以单线程模式，SIMD（单指令，多数据）模式和MIMD（多指令，多数据）模式交替运行的数字处理器的并行处理架构。 用于处理器的指令集包括用于在模式之间切换和在并行处理路径之间交换数据的指令。 任何指令路径中的硬件或未使用的指令路径的部分被禁用以节省电力。