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公开(公告)号：US08377786B2
公开(公告)日：2013-02-19
申请号：US13020369
申请日：2011-02-03
IPC分类号： H01L21/311 , H01L21/3115
CPC分类号： H01L21/31155 , H01L21/31111 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823807 , H01L21/823814 , H01L21/823864
摘要： Embodiments of methods for fabricating the semiconductor devices are provided. The method includes forming a layer of spacer material over a semiconductor region that includes a first gate electrode structure and a second gate electrode structure. Carbon is introduced into a portion of the layer covering the semiconductor region about the first gate electrode structure or the second gate electrode structure. The layer is etched to form a first sidewall spacer about the first gate electrode structure and a second sidewall spacer about the second gate electrode structure.
摘要翻译： 提供了制造半导体器件的方法的实施例。 该方法包括在包括第一栅电极结构和第二栅电极结构的半导体区上形成间隔物层。 将碳引入围绕第一栅电极结构或第二栅电极结构覆盖半导体区的层的一部分。 蚀刻该层以围绕第一栅极电极结构形成第一侧壁隔离物，并围绕第二栅电极结构形成第二侧壁隔离物。
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2.发明申请Reduction of Defect Rates in PFET Transistors Comprising a Silicon/Germanium Semiconductor Material by Providing a Graded Germanium Concentration 审中-公开通过提供分级锗浓度来减少包含硅/锗半导体材料的PFET晶体管中的缺陷率公开(公告)号：US20120161249A1
公开(公告)日：2012-06-28
申请号：US13338349
申请日：2011-12-28
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/513 , H01L29/518 , H01L29/6659 , H01L29/66651 , H01L29/7833
摘要： When forming sophisticated gate electrode structures in an early manufacturing stage, the threshold voltage characteristics may be adjusted on the basis of a semiconductor alloy, which may be formed on the basis of low pressure CVD techniques. In order to obtain a desired high band gap offset, for instance with respect to a silicon/germanium alloy, a moderately high germanium concentration may be provided within the semiconductor alloy, wherein, however, at the interface formed with the semiconductor base material, a low germanium concentration may significantly reduce the probability of creating dislocation defects.
摘要翻译： 当在早期制造阶段形成复杂的栅电极结构时，可以基于可以基于低压CVD技术形成的半导体合金来调整阈值电压特性。 为了获得期望的高带隙偏移，例如对于硅/锗合金，可以在半导体合金内提供适度高的锗浓度，然而，在与半导体基底材料形成的界面处， 低锗浓度可能会显着降低产生位错缺陷的可能性。
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3.发明授权Reducing defect rate during deposition of a channel semiconductor alloy into an in situ recessed active region 有权在将沟道半导体合金沉积到原位凹入的有源区域中降低缺陷率公开(公告)号：US08836047B2
公开(公告)日：2014-09-16
申请号：US13421394
申请日：2012-03-15
IPC分类号： H01L27/04 , H01L21/8238 , H01L21/84 , H01L21/8234 , H01L21/762 , H01L27/12
CPC分类号： H01L21/84 , H01L21/76283 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
摘要翻译： 当基于阈值电压调节半导体合金形成复杂的高k金属栅电极结构时，可以应用高效的原位工艺技术，以便在专用有源区域中形成凹槽并用半导体合金再填充凹槽。 为了在活性区域的凹陷期间减少或避免蚀刻相关的不规则性，可以控制在先前处理期间，特别是在形成沟槽隔离区域期间的铝污染程度。
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4.发明授权Differential threshold voltage adjustment in PMOS transistors by differential formation of a channel semiconductor material 有权通过沟道半导体材料的差分形成，PMOS晶体管中的差分阈值电压调整公开(公告)号：US08536009B2
公开(公告)日：2013-09-17
申请号：US13197239
申请日：2011-08-03
IPC分类号： H01L21/8234
CPC分类号： H01L21/823412 , H01L21/823456 , H01L21/823807 , H01L21/82385
摘要： In sophisticated semiconductor devices, high-k metal gate electrode structures may be provided in an early manufacturing stage wherein the threshold voltage adjustment for P-channel transistors may be accomplished on the basis of a threshold voltage adjusting semiconductor alloy, such as a silicon/germanium alloy, for long channel devices, while short channel devices may be masked during the selective epitaxial growth of the silicon/germanium alloy. In some illustrative embodiments, the threshold voltage adjustment may be accomplished without any halo implantation processes for the P-channel transistors, while the threshold voltage may be tuned by halo implantations for the N-channel transistors.
摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段提供高k金属栅极电极结构，其中P沟道晶体管的阈值电压调节可以基于阈值电压调节半导体合金（诸如硅/锗） 合金，用于长沟道器件，而在硅/锗合金的选择性外延生长期间可能会掩蔽短沟道器件。 在一些说明性实施例中，阈值电压调整可以在没有用于P沟道晶体管的任何晕圈注入工艺的情况下完成，而阈值电压可以通过N沟道晶体管的晕圈注入来调节。
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5.发明申请Transistor Comprising High-K Metal Gate Electrode Structures Including a Polycrystalline Semiconductor Material and Embedded Strain-Inducing Semiconductor Alloys 有权晶体管包括包含多晶半导体材料和嵌入式应变诱导半导体合金的高K金属栅电极结构公开(公告)号：US20120161250A1
公开(公告)日：2012-06-28
申请号：US13198209
申请日：2011-08-04
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814
摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.
摘要翻译： 当在硅/锗半导体合金的基础上在早期制造阶段形成复杂的高k金属栅极电极结构以调整沟道区域中适当的电子条件时，应变诱导嵌入式半导体合金如硅 /锗合金，可以通过在栅极图案化工艺之后在栅电极结构的硅材料中引发晶体生长来增强。 以这种方式，可以减小或补偿阈值电压调节硅/锗合金的负应变。
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6.发明授权Superior integrity of high-k metal gate stacks by preserving a resist material above end caps of gate electrode structures 有权通过在栅极电极结构的端盖上方保留抗蚀材料，可以实现高k金属栅极叠层的完整性公开(公告)号：US08481381B2
公开(公告)日：2013-07-09
申请号：US13232711
申请日：2011-09-14
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L22/10 , H01L21/823807 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L29/7848 , Y02P80/30
摘要： When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
摘要翻译： 在基于晶体管的基础上在半导体器件中形成高k金属栅极电极结构时，可以避免在N沟道晶体管的栅电极结构的端部处敏感材料的过度曝光，例如，在 在将应变诱导半导体材料并入P沟道晶体管的有源区域中，从而有助于提高预定晶体管特性和性能的产量。
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7.发明申请REDUCING DEFECT RATE DURING DEPOSITION OF A CHANNEL SEMICONDUCTOR ALLOY INTO AN IN SITU RECESSED ACTIVE REGION 有权在通道半导体合金沉积在现场的有源区域中减少缺陷率公开(公告)号：US20120235249A1
公开(公告)日：2012-09-20
申请号：US13421394
申请日：2012-03-15
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/84 , H01L21/76283 , H01L21/823412 , H01L21/823481 , H01L21/823807 , H01L21/823878 , H01L27/1203
摘要： When forming sophisticated high-k metal gate electrode structures on the basis of a threshold voltage adjusting semiconductor alloy, a highly efficient in situ process technique may be applied in order to form a recess in dedicated active regions and refilling the recess with a semiconductor alloy. In order to reduce or avoid etch-related irregularities during the recessing of the active regions, the degree of aluminum contamination during the previous processing, in particular during the formation of the trench isolation regions, may be controlled.
摘要翻译： 当基于阈值电压调节半导体合金形成复杂的高k金属栅电极结构时，可以应用高效的原位工艺技术，以便在专用有源区域中形成凹槽并用半导体合金再填充凹槽。 为了在活性区域的凹陷期间减少或避免蚀刻相关的不规则性，可以控制在先前处理期间，特别是在形成沟槽隔离区域期间的铝污染程度。
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8.发明申请Superior Integrity of High-K Metal Gate Stacks by Preserving a Resist Material Above End Caps of Gate Electrode Structures 有权通过保护栅极电极结构的端盖上方的抗蚀材料，可以实现高K金属栅极堆叠的完整性公开(公告)号：US20130065329A1
公开(公告)日：2013-03-14
申请号：US13232711
申请日：2011-09-14
IPC分类号： H01L21/66 , H01L21/20 , H01L21/336
CPC分类号： H01L22/10 , H01L21/823807 , H01L21/823842 , H01L21/823871 , H01L21/823878 , H01L29/7848 , Y02P80/30
摘要： When forming high-k metal gate electrode structures in a semiconductor device on the basis of a basic transistor design, undue exposure of sensitive materials at end portions of the gate electrode structures of N-channel transistors may be avoided, for instance, prior to and upon incorporating a strain-inducing semiconductor material into the active region of P-channel transistors, thereby contributing to superior production yield for predefined transistor characteristics and performance.
摘要翻译： 在基于晶体管的基础上在半导体器件中形成高k金属栅极电极结构时，可以避免在N沟道晶体管的栅电极结构的端部处敏感材料的过度曝光，例如，在 在将应变诱导半导体材料并入P沟道晶体管的有源区域中，从而有助于提高预定晶体管特性和性能的产量。
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9.发明授权Method for forming a transistor comprising high-k metal gate electrode structures including a polycrystalline semiconductor material and embedded strain-inducing semiconductor alloys 有权一种用于形成包括包括多晶半导体材料和嵌入式应变诱导半导体合金的高k金属栅电极结构的晶体管的方法公开(公告)号：US08343826B2
公开(公告)日：2013-01-01
申请号：US13198209
申请日：2011-08-04
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814
摘要： When forming sophisticated high-k metal gate electrode structures in an early manufacturing stage on the basis of a silicon/germanium semiconductor alloy for adjusting appropriate electronic conditions in the channel region, the efficiency of a strain-inducing embedded semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by initiating a crystal growth in the silicon material of the gate electrode structure after the gate patterning process. In this manner, the negative strain of the threshold voltage adjusting silicon/germanium alloy may be reduced or compensated for.
摘要翻译： 当在硅/锗半导体合金的基础上在早期制造阶段形成复杂的高k金属栅极电极结构以调整沟道区域中适当的电子条件时，应变诱导嵌入式半导体合金如硅 /锗合金，可以通过在栅极图案化工艺之后在栅电极结构的硅材料中引发晶体生长来增强。 以这种方式，可以减小或补偿阈值电压调节硅/锗合金的负应变。
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10.发明申请TRANSISTORS WITH EMBEDDED STRAIN-INDUCING MATERIAL FORMED IN CAVITIES PROVIDED BY AN OXIDIZING ETCH PROCESS 有权具有嵌入式应变诱导材料的晶体管通过氧化蚀刻工艺提供的CAVIITY公开(公告)号：US20120306027A1
公开(公告)日：2012-12-06
申请号：US13483630
申请日：2012-05-30
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7848 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/41775 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7834
摘要： When forming sophisticated semiconductor devices including transistors with sophisticated high-k metal gate electrode structures and a strain-inducing semiconductor alloy, transistor uniformity and performance may be enhanced by providing superior growth conditions during the selective epitaxial growth process. To this end, a semiconductor material may be preserved at the isolation regions in order to avoid the formation of pronounced shoulders. Furthermore, in some illustrative embodiments, additional mechanisms are implemented in order to avoid undue material loss, for instance upon removing a dielectric cap material and the like.
摘要翻译： 当形成具有复杂的高k金属栅电极结构的晶体管和应变诱导半导体合金的复杂半导体器件时，可以通过在选择性外延生长工艺期间提供优异的生长条件来增强晶体管的均匀性和性能。 为此，可以在隔离区域保留半导体材料，以避免突出的肩部的形成。 此外，在一些说明性实施例中，为了避免不适当的材料损失，例如在去除电介质盖材料等时，实施附加机构。
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