利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

48 条记录 (耗时 0.03 秒)

    OPC trimming for performance
    1.
    发明授权
    OPC trimming for performance 失效
    OPC修剪性能

    公开(公告)号：US07627836B2

    公开(公告)日：2009-12-01

    申请号：US11164044

    申请日：2005-11-08

    申请人： James A. Culp ,  Lars W. Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen L. Runyon ,  Patrick M. Williams

    发明人： James A. Culp ,  Lars W. Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen L. Runyon ,  Patrick M. Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

    摘要翻译： 基于使用光学邻近校正技术的方法，在芯片制造之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

    OPC TRIMMING FOR PERFORMANCE
    2.
    发明申请
    OPC TRIMMING FOR PERFORMANCE 失效

    公开(公告)号：US20070106968A1

    公开(公告)日：2007-05-10

    申请号：US11164044

    申请日：2005-11-08

    申请人： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

    发明人： James Culp ,  Lars Liebmann ,  Rajeev Malik ,  K. Paul Muller ,  Shreesh Narasimha ,  Stephen Runyon ,  Patrick Williams

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： An iterative timing analysis is analytically performed before a chip is fabricated, based on a methodology using optical proximity correction techniques for shortening the gate lengths and adjusting metal line widths and proximity distances of critical time sensitive devices. The additional mask is used as a selective trim to form shortened gate lengths or wider metal lines for the selected, predetermined transistors, affecting the threshold voltages and the RC time constants of the selected devices. Marker shapes identify a predetermined subgroup of circuitry that constitutes the devices in the critical timing path. The analysis methodology is repeated as often as needed to improve the timing of the circuit with shortened designed gate lengths and modified RC timing constants until manufacturing limits are reached. A mask is made for the selected critical devices using OPC techniques.

    摘要翻译： 基于使用光学邻近校正技术的方法，在制造芯片之前分析地执行迭代时序分析，以缩短栅极长度并调整关键时间敏感器件的金属线宽度和接近距离。 附加掩模用作选择性修整以形成用于所选择的预定晶体管的缩短的栅极长度或更宽的金属线，影响所选器件的阈值电压和RC时间常数。 标记形状识别构成关键定时路径中的装置的电路的预定子组。 根据需要经常重复分析方法，以在缩短设计的栅极长度和修改的RC定时常数的情况下改善电路的时序，直到达到制造限值。 使用OPC技术为所选的关键设备制作掩码。

    PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SEMICONDUCTOR DEVICE
    3.
    发明申请
    PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SEMICONDUCTOR DEVICE 失效
    在半导体器件的高比例电介质区域中防止蚀刻

    公开(公告)号：US20080303070A1

    公开(公告)日：2008-12-11

    申请号：US12190777

    申请日：2008-08-13

    申请人： Paul D. Agnello ,  Rajeev Malik ,  K. Paul Muller

    发明人： Paul D. Agnello ,  Rajeev Malik ,  K. Paul Muller

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475

    摘要： Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.

    摘要翻译： 公开了用于防止在半导体器件中的高纵横比介电区域中的空化的方法以及如此形成的器件。 本发明包括在一对结构之间的高纵横比电介质区域中沉积第一电介质，然后移除第一电介质以形成邻近每个结构的支承表面。 轴承表面防止随后填充高纵横比区域的层间电介质的空化。

    REDUCED SOFT ERROR RATE THROUGH METAL FILL AND PLACEMENT
    8.
    发明申请
    REDUCED SOFT ERROR RATE THROUGH METAL FILL AND PLACEMENT 有权
    通过金属填充和放置减少软错误率

    公开(公告)号：US20100301463A1

    公开(公告)日：2010-12-02

    申请号：US12473435

    申请日：2009-05-28

    申请人： K. Paul Muller ,  Alicia Wang

    发明人： K. Paul Muller ,  Alicia Wang

    IPC分类号： H01L23/556 ,  H01L21/71

    CPC分类号： H01L23/556 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for reducing single event upsets in an integrated circuit includes the step of providing a plurality of levels within the integrated circuit, wherein the plurality of levels within the integrated circuit are in a stacked arrangement. The method also includes the step of providing a plurality of metal fill patterns within each of the plurality of levels within the integrated circuit. The method further includes the step of placing the plurality of metal fill patterns within at least one of the plurality of levels in a pattern such that a line of sight towards an active silicon layer does not exist within the stacked arrangement of the plurality of levels, thereby increasingly absorbing ionizing radiation particles, and thereby reducing single event upsets in the integrated circuit.

    摘要翻译： 一种用于减少集成电路中的单事件扰乱的方法包括在集成电路内提供多个电平的步骤，其中集成电路内的多个电平处于堆叠布置。 该方法还包括在集成电路内的多个电平的每一个内提供多个金属填充图案的步骤。 该方法还包括将多个金属填充图案放置在多个层中的至少一个层中的图案的步骤，使得朝向有源硅层的视线不存在于多个层次的堆叠布置中， 从而越来越多地吸收电离辐射颗粒，从而减少集成电路中的单个事件的不适。

    Alignment insensitive D-cache cell
    9.
    发明授权
    Alignment insensitive D-cache cell 有权
    对齐不敏感的D缓存单元

    公开(公告)号：US07304352B2

    公开(公告)日：2007-12-04

    申请号：US11111454

    申请日：2005-04-21

    申请人： K. Paul Muller ,  Kevin A. Batson ,  Michael J. Lee

    发明人： K. Paul Muller ,  Kevin A. Batson ,  Michael J. Lee

    IPC分类号： H01L29/76 ,  H01L29/94

    CPC分类号： G11C11/412 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903 ,  Y10S257/904

    摘要： A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.

    摘要翻译： 具有改进的示意图和布局设计的D缓存SRAM单元，其显示出来自电路原理图和物理单元布局视角的增加的对称性。 也就是说，SRAM单元包括两个读取端口，并且通过在真实侧提供一个读取端口和在补充端上提供一个读取端口来最小化不对称性。 通过从本地互连级别提供通向M1或金属化级别的通孔连接，通过从真实和补偿侧两者的交叉耦合上升到一个级别，不对称性在布局中另外最小化。 此外，局部互连（MC）和栅极导体结构（PC）之间的距离已经在交叉锁存SRAM单元中的每个pFET被放大和均衡。 因此，通过最大化这个MC-PC距离，SRAM单元已经对覆盖（局部互连处理太近）变得不敏感。

    Double gated vertical transistor with different first and second gate materials
    10.
    发明授权
    Double gated vertical transistor with different first and second gate materials 失效
    双门控垂直晶体管，具有不同的第一和第二栅极材料

    公开(公告)号：US06960806B2

    公开(公告)日：2005-11-01

    申请号：US09886823

    申请日：2001-06-21

    申请人： Andres Bryant ,  Meikei Ieong ,  K. Paul Muller ,  Edward J. Nowak ,  David M. Fried ,  Jed Rankin

    发明人： Andres Bryant ,  Meikei Ieong ,  K. Paul Muller ,  Edward J. Nowak ,  David M. Fried ,  Jed Rankin

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76

    CPC分类号： H01L29/4908 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66795 ,  H01L29/785

    摘要： Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and −0.5V for pFETs.

    摘要翻译： 因此，本发明提供一种双门控晶体管及其形成方法，其导致改进的器件性能和密度。 本发明的优选实施例提供了具有不对称栅极掺杂的双门控晶体管，其中双栅极中的一个被简并掺杂为n型，另一个为简并p型。 通过掺杂栅极n型和另一种p型，所得器件的阈值电压得到改善。 特别地，通过不对称地掺杂两个栅极，所得到的晶体管可以通过适当掺杂的体，在允许低电压CMOS操作的范围内具有阈值电压。 例如，可以产生对于nFET具有在0V和0.5V之间的阈值电压并且对于pFET而言在0和-0.5V之间的晶体管。