公开(公告)号：US5667586A

公开(公告)日：1997-09-16

申请号：US626115

申请日：1996-04-01

申请人： Bruce Allen Ek ,  Stephen McConnell Gates ,  Fernando Jose Guarin ,  Subramanian Srikanteswara Iyer ,  Adrian Roger Powell

发明人： Bruce Allen Ek ,  Stephen McConnell Gates ,  Fernando Jose Guarin ,  Subramanian Srikanteswara Iyer ,  Adrian Roger Powell

IPC分类号： H01L21/02 ,  H01L21/04 ,  H01L21/20 ,  H01L27/12 ,  H01L31/10 ,  H01L31/18 ,  H01L33/00 ,  H01S5/00 ,  H01S5/323 ,  C30B25/02

CPC分类号： H01L33/007 ,  H01L21/0445 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

摘要： A structure is fabricated comprising a substrate, a dielectric layer formed over the substrate, and a single crystal layer of a compound formed over the dielectric layer. The single crystal layer is formed by the chemical reaction of at least a first element with an initial single crystal layer of a second element on the dielectric layer having an initial thickness of about 100 to about 10,000 angstroms.According to another aspect, a carbide single crystal layer is provided on a substrate by depositing carbon from a solid carbon source at a low rate and low temperature, followed by reacting the carbon with the underlying layer to convert it to the carbide.

摘要翻译： 制造的结构包括衬底，在衬底上形成的电介质层和在电介质层上形成的化合物的单晶层。 单晶层通过至少第一元素与电介质层上初始厚度为约100至约10,000埃的第二元素的初始单晶层的化学反应形成。 根据另一方面，通过在低速率和低温下从固体碳源沉积碳，然后使碳与下层反应以将其转化为碳化物，在基板上提供碳化物单晶层。

公开(公告)号：US07682896B2

公开(公告)日：2010-03-23

申请号：US11750355

申请日：2007-05-18

申请人： Herbert Lei Ho ,  Subramanian Srikanteswara Iyer ,  Vidhya Ramachandran

发明人： Herbert Lei Ho ,  Subramanian Srikanteswara Iyer ,  Vidhya Ramachandran

IPC分类号： H01L21/8242 ,  H01L21/331

CPC分类号： H01L27/10861 ,  H01L28/91 ,  H01L29/945

摘要： The present invention relates to a method of fabrication process which integrates the processing steps for fabricating the trench MIM capacitor with the conventional middle-of-line processing steps for fabricating metal contacts, so that the inner metallic electrode layer of the trench MIM capacitor and the metal contact of the FET or other logic circuitry components are formed by a single middle-of-line processing step and comprise essentially the same metallic material. The semiconductor device contains at least one trench metal-oxide-metal (MIM) capacitor and at least one other logic circuitry component, preferably at least one field effect transistor (FET). The trench MIM capacitor is located in a trench in a substrate and comprises inner and outer metallic electrode layers with a dielectric layer therebetween. The FET comprises a source region, a drain region, a channel region, and at least one metal contact connected with the source or drain region.

摘要翻译： 本发明涉及一种制造工艺的方法，该方法将用于制造沟槽MIM电容器的处理步骤与用于制造金属触点的常规中间线处理步骤相结合，使得沟槽MIM电容器的内部金属电极层和 FET或其他逻辑电路部件的金属接触通过单个中间线处理步骤形成并且包括基本上相同的金属材料。 半导体器件包含至少一个沟槽金属氧化物金属（MIM）电容器和至少一个其它逻辑电路部件，优选地至少一个场效应晶体管（FET）。 沟槽MIM电容器位于衬底中的沟槽中，并且包括其间具有介电层的内部和外部金属电极层。 FET包括源极区，漏极区，沟道区以及与源极或漏极区连接的至少一个金属接触。

公开(公告)号：US5759898A

公开(公告)日：1998-06-02

申请号：US770065

申请日：1996-12-19

申请人： Bruce A. Ek ,  Subramanian Srikanteswara Iyer ,  Philip Michael Pitner ,  Adrian R. Powell ,  Manu Jamndas Tejwani

发明人： Bruce A. Ek ,  Subramanian Srikanteswara Iyer ,  Philip Michael Pitner ,  Adrian R. Powell ,  Manu Jamndas Tejwani

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01L21/324 ,  H01L27/12 ,  H01L21/201

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502

摘要： A process and method for producing strained and defect free semiconductor layers. In a preferred embodiment, silicon on insulator may be used as a substrate for the growth of fully relaxed SiGe buffer layers. A new strain relief mechanism operates, whereby the SiGe layer relaxes without the generation of threading dislocations within the SiGe layer. This is achieved by depositing SiGe on an SOI substrate with a superficial silicon thickness. Initially the strain in the SiGe layer becomes equalized with the thin Si layer by creating tensile strain in the Si layer. Then the strain created in the thin Si layer is relaxed by plastic deformation during an anneal. Since dislocations are formed, and glide in the thin Si layer, threading dislocations are not introduced into the upper SiGe material. A strained silicon layer for heterostructures may then be formed on the SiGe material.

摘要翻译： 一种制造应变和无缺陷半导体层的方法和方法。 在优选实施例中，绝缘体上硅可以用作用于生长完全松弛的SiGe缓冲层的衬底。 新的应变消除机构工作，由此SiGe层松弛而不在SiGe层内产生穿透位错。 这通过在具有表面硅厚度的SOI衬底上沉积SiGe来实现。 最初，通过在Si层中产生拉伸应变，SiGe层中的应变与薄Si层相等。 那么在薄Si层中产生的应变在退火过程中被塑性变形所松弛。 由于形成位错，并且在薄的Si层中滑动，所以穿透位错不会引入上部SiGe材料。 然后可以在SiGe材料上形成用于异质结构的应变硅层。