公开(公告)号：US20070002617A1

公开(公告)日：2007-01-04

申请号：US11171033

申请日：2005-06-30

Applicant: Theodore Houston ,  David Scott ,  Sudha Thiruvengadam

Inventor： Theodore Houston ,  David Scott ,  Sudha Thiruvengadam

IPC: G11C11/34

CPC classification number: G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: An SRAM array and a dummy cell row structure is discussed that permits an SRAM array to be divided into segments isolated by a row pattern of dummy cells. The dummy cell structure avoids the use of special OPC conditions at the power supply line and block boundaries by providing a continuous cell array at the lower cell patterning levels in an area efficient implementation. In one implementation, the SRAM array comprises a first and second array block each comprising an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells. Beneficially, the bitlines of the array may be continuous across the first and second array blocks and a dummy cell associated therewith.

Abstract translation: 讨论了SRAM阵列和虚拟单元行结构，其允许将SRAM阵列划分成由虚拟单元的行图案隔离的段。 虚拟单元结构避免了在电源线和块边界处使用特殊的OPC条件，通过在区域有效的实现中在较低单元图案化级别提供连续的单元阵列。 在一个实现中，SRAM阵列包括第一和第二阵列块，每个阵列块包括具有第一布局配置的SRAM单元，一个或多个虚拟单元具有沿着与SRAM阵列的字线相关联的行图案布置的第二布局配置 连接到第一阵列块的第一电源电压线和连接到第二阵列块的第二不同电源电压线。 阵列块的第一和第二电源电压线还连接到一个或多个虚设单元。 有利的是，阵列的位线可以在第一和第二阵列块和与其相关联的虚拟单元中是连续的。

公开(公告)号：US20090046519A1

公开(公告)日：2009-02-19

申请号：US11839464

申请日：2007-08-15

Applicant: Alice Wang ,  David Scott ,  Sumanth Gururajarao ,  Gordon Gammie ,  Sudha Thiruvengadam

Inventor： Alice Wang ,  David Scott ,  Sumanth Gururajarao ,  Gordon Gammie ,  Sudha Thiruvengadam

IPC: G11C5/14

CPC classification number: G11C29/006 ,  G11C11/41 ,  G11C29/50

Abstract: A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing.

Abstract translation: 一种用于配置用于操作的静态随机存取存储器（SRAM）位单元的计算机实现的方法，自适应偏置装置和半导体晶片测试系统。 在一个实施例中，该方法包括：（1）确定晶片上的SRAM位单元的性能特性，（2）将性能特性与目标进行比较，以及（3）基于所述SRAM位单元配置与SRAM位单元相关联的偏置电路 比较。

公开(公告)号：US07474582B2

公开(公告)日：2009-01-06

申请号：US11637352

申请日：2006-12-12

Applicant: Hugh Thomas Mair ,  James Sangwon Song ,  Franck Benjamin Dahan ,  William Douglas Wilson ,  Norman LeRoy Culp ,  Sudha Thiruvengadam

Inventor： Hugh Thomas Mair ,  James Sangwon Song ,  Franck Benjamin Dahan ,  William Douglas Wilson ,  Norman LeRoy Culp ,  Sudha Thiruvengadam

IPC: G11C5/14 ,  G11C11/00 ,  G11C7/06

CPC classification number: G11C5/147 ,  G11C5/143 ,  G11C2207/2227

Abstract: One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first voltage with a reference voltage. The first voltage can correspond to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit. The reference voltage can correspond to a minimum threshold voltage for read/write operations of the memory array. The system also comprises an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator. The output voltage can be the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage.

Abstract translation: 本发明的一个实施例包括用于管理存储器阵列的功率的系统。 该系统包括比较器，其被配置为将第一电压与参考电压进行比较。 第一电压可以对应于与存储器阵列相关联的外围电路中的至少一个的工作电压和被配置为与外围电路通信的逻辑电路。 参考电压可以对应于存储器阵列的读/写操作的最小阈值电压。 该系统还包括输出电路，其配置为响应于比较器的输出向存储器阵列提供输出电压。 输出电压可以是外围电路和逻辑电路中的至少一个的工作电压的最大值和最小阈值电压。

公开(公告)号：US07376038B2

公开(公告)日：2008-05-20

申请号：US11385151

申请日：2006-03-21

Applicant: Sudha Thiruvengadam ,  Ramaprasath Vilangudipitchai ,  David B. Scott ,  Uming U. Ko ,  Alice Wang

Inventor： Sudha Thiruvengadam ,  Ramaprasath Vilangudipitchai ,  David B. Scott ,  Uming U. Ko ,  Alice Wang

IPC: G11C5/14

CPC classification number: G11C8/10

Abstract: A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.

Abstract translation: 一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。 存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。 控制逻辑向存储器提供目标位单元的地址。 在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

公开(公告)号：US5572536A

公开(公告)日：1996-11-05

申请号：US249482

申请日：1994-05-26

Applicant: Sudha Thiruvengadam

Inventor： Sudha Thiruvengadam

IPC: G06F11/27 ,  G01R31/317

CPC classification number: G06F11/27 ,  G06F2201/83

Abstract: Digital circuitry in a data processing system includes parallel signature analysis circuitry having a sampling feature which permits sampling any given signal on all clock phases of the digital circuitry. The parallel signature analysis circuitry provides for selective coupling of a target node to each of the respective inputs of a pair of serially-coupled latches.

Abstract translation: 数据处理系统中的数字电路包括具有采样特征的并行签名分析电路，其允许对数字电路的所有时钟相位上的任何给定信号进行采样。 并行签名分析电路提供目标节点与一对串联耦合的锁存器的各个输入中的每一个的选择性耦合。

公开(公告)号：US20070223294A1

公开(公告)日：2007-09-27

申请号：US11385151

申请日：2006-03-21

Applicant: Sudha Thiruvengadam ,  Ramaprasath Vilangudipitchai ,  David Scott ,  Uming Ko ,  Alice Wang

Inventor： Sudha Thiruvengadam ,  Ramaprasath Vilangudipitchai ,  David Scott ,  Uming Ko ,  Alice Wang

IPC: G11C7/00

CPC classification number: G11C8/10

Abstract: A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.

Abstract translation: 一种包括控制逻辑和耦合到控制逻辑的存储器的计算机系统。 存储器包括用于在控制逻辑和位单元之间传送数据的多个比特单元和位线。 控制逻辑向存储器提供目标位单元的地址。 在单个时钟周期内，存储器使用地址来激活目标比特单元，以预先耦合到目标比特单元的位线，并访问目标比特单元。

公开(公告)号：US20080137444A1

公开(公告)日：2008-06-12

申请号：US11637352

申请日：2006-12-12

Applicant: Hugh Thomas Mair ,  James Sangwon Song ,  Franck Benjamin Dahan ,  William Douglas Wilson ,  Norman LeRoy Culp ,  Sudha Thiruvengadam

Inventor： Hugh Thomas Mair ,  James Sangwon Song ,  Franck Benjamin Dahan ,  William Douglas Wilson ,  Norman LeRoy Culp ,  Sudha Thiruvengadam

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C5/147 ,  G11C5/143 ,  G11C2207/2227

Abstract: One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first voltage with a reference voltage. The first voltage can correspond to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit. The reference voltage can correspond to a minimum threshold voltage for read/write operations of the memory array. The system also comprises an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator. The output voltage can be the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage.

Abstract translation: 本发明的一个实施例包括用于管理存储器阵列的功率的系统。 该系统包括比较器，其被配置为将第一电压与参考电压进行比较。 第一电压可以对应于与存储器阵列相关联的外围电路中的至少一个的工作电压和被配置为与外围电路通信的逻辑电路。 参考电压可以对应于存储器阵列的读/写操作的最小阈值电压。 该系统还包括输出电路，其配置为响应于比较器的输出向存储器阵列提供输出电压。 输出电压可以是外围电路和逻辑电路中的至少一个的工作电压的最大值和最小阈值电压。

公开(公告)号：US07236396B2

公开(公告)日：2007-06-26

申请号：US11171033

申请日：2005-06-30

Applicant: Theodore W. Houston ,  David Barry Scott ,  Sudha Thiruvengadam

Inventor： Theodore W. Houston ,  David Barry Scott ,  Sudha Thiruvengadam

IPC: G11C11/34

CPC classification number: G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first and second array block each including an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.

Abstract translation: 具有虚拟单元行结构的SRAM阵列，其中SRAM阵列被划分成由虚设单元的行图案隔离的段。 虚拟单元结构在较低单元图案化水平下提供连续的单元阵列。 SRAM阵列包括第一和第二阵列块，每个第一和第二阵列块包括具有第一布局配置的SRAM单元，一个或多个虚拟单元具有沿着与SRAM阵列的字线相关联的行图案布置的第二布局配置，第一功率 连接到第一阵列块的电源电压线和连接到第二阵列块的第二不同电源电压线。 阵列块的第一和第二电源电压线还连接到一个或多个虚设单元。

公开(公告)号：US5710780A

公开(公告)日：1998-01-20

申请号：US695139

申请日：1996-08-08

Applicant: Sudha Thiruvengadam

Inventor： Sudha Thiruvengadam

IPC: G06F11/27 ,  G01R31/317

CPC classification number: G06F11/27 ,  G06F2201/83

Abstract: Digital circuitry (11) in a data processing system (10) includes parallel signature analysis circuitry (49, 49A) having a sampling feature (51, 53, 89) which permits sampling any given signal on all clock phases of the digital circuitry.

Abstract translation: 数据处理系统（10）中的数字电路（11）包括具有采样特征（51,53,89）的并行签名分析电路（49,49A），其允许对数字电路的所有时钟相位上的任何给定信号进行采样。