公开(公告)号：US20150340374A1

公开(公告)日：2015-11-26

申请号：US14642668

申请日：2015-03-09

Applicant: Won Seok JUNG ,  Joon Hee LEE ,  Keon Soo KIM ,  Sun Yeong LEE

Inventor： Won Seok JUNG ,  Joon Hee LEE ,  Keon Soo KIM ,  Sun Yeong LEE

IPC: H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L21/28008 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.

Abstract translation: 一种制造存储器件的方法包括：提供衬底; 在单元区域中形成沿垂直于所述衬底的上表面的方向延伸的沟道;以及多个栅极电极层和多个绝缘层，所述绝缘层交替地堆叠在所述衬底上以与所述沟道相邻; 在设置在单元区域的外围的外围电路区域在基板上形成多个电路元件; 以及在所述单元区域和所述外围电路区域中的所述基板上形成层间绝缘层，所述层间绝缘层包括覆盖所述多个电路元件的第一，底部层间绝缘层和所述多个栅电极层的至少一部分， 以及设置在所述第一层间绝缘层上的第二顶层间绝缘层。

公开(公告)号：US20150214242A1

公开(公告)日：2015-07-30

申请号：US14464727

申请日：2014-08-21

Applicant: Sun-Yeong Lee

Inventor： Sun-Yeong Lee

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A vertical non-volatile memory device includes gate electrodes stacked in a first region of a substrate in a third direction perpendicular to a top surface of the substrate including the first region and a second region surrounding the first region, a channel extending in the third direction through the gate electrodes, conductive pads extending from the gate electrodes, respectively, in a first direction parallel to the top surface of the substrate in the second region, insulation pads extending from the gate electrodes and the conductive pads, respectively, in a second direction perpendicular to the first direction in the second region, contact plugs electrically connected to the conductive pads, respectively, and a first reference structure under at least one of the insulation pads in the second region.

Abstract translation: 垂直非易失性存储器件包括在垂直于包括第一区域的衬底的顶表面垂直的第三方向上的衬底的第一区域中堆叠的栅电极和围绕第一区域的第二区域，沿第三方向延伸的沟道 通过栅极电极，在与第二区域的基板的顶面平行的第一方向分别从栅电极延伸的导电焊盘，绝缘焊盘分别从第二方向从栅电极和导电焊盘延伸 在所述第二区域中垂直于所述第一方向，分别电连接到所述导电焊盘的接触插塞和位于所述第二区域中的至少一个所述绝缘焊盘下方的第一参考结构。