公开(公告)号：US09666592B2

公开(公告)日：2017-05-30

申请号：US14861262

申请日：2015-09-22

Applicant: Tae Hwan Yun ,  Joon Hee Lee ,  Ji Young Kim

Inventor： Tae Hwan Yun ,  Joon Hee Lee ,  Ji Young Kim

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L21/822 ,  H01L21/8229

CPC classification number: H01L27/1157 ,  H01L21/8221 ,  H01L21/8229 ,  H01L27/11582

Abstract: A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure. The isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions.

公开(公告)号：US09640549B2

公开(公告)日：2017-05-02

申请号：US14534181

申请日：2014-11-06

Applicant: Seok-Won Lee ,  Joon-Hee Lee ,  Dong-Seog Eun ,  Chang-Hyun Lee

Inventor： Seok-Won Lee ,  Joon-Hee Lee ,  Dong-Seog Eun ,  Chang-Hyun Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11548 ,  H01L27/11575 ,  G11C8/14 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

公开(公告)号：US20160149010A1

公开(公告)日：2016-05-26

申请号：US15012979

申请日：2016-02-02

Applicant: Jin-Yeon WON ,  Joon-Hee LEE ,  Seung-Woo PAEK ,  Dong-Seog EUN

Inventor： Jin-Yeon WON ,  Joon-Hee LEE ,  Seung-Woo PAEK ,  Dong-Seog EUN

IPC: H01L29/423 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/42344 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

Abstract: According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

Abstract translation: 根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。 堆叠结构在衬底上限定通孔。 栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。 通道图案可以在通孔中。 隧道层可围绕通道图案。 电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。 保护图案可以在栅电极的第一部分和电荷陷阱层之间。

公开(公告)号：US09136432B2

公开(公告)日：2015-09-15

申请号：US13997873

申请日：2011-12-06

Applicant: Jun Ho Yun ,  Ki Bum Nam ,  Joon Hee Lee ,  Chang Youn Kim ,  Hong Jae Yoo ,  Sung Hoon Hong

Inventor： Jun Ho Yun ,  Ki Bum Nam ,  Joon Hee Lee ,  Chang Youn Kim ,  Hong Jae Yoo ,  Sung Hoon Hong

IPC: H01L33/14 ,  H01L33/38 ,  H01L33/40 ,  H01L33/00 ,  H01L33/22 ,  H01L33/44

CPC classification number: H01L33/14 ,  H01L33/0079 ,  H01L33/22 ,  H01L33/38 ,  H01L33/405 ,  H01L33/44

Abstract: Disclosed herein is a high efficiency light emitting diode. The light emitting diode includes: a semiconductor stack positioned over a support substrate; a reflective metal layer positioned between the support substrate and the semiconductor stack to ohmic-contact a p-type compound semiconductor layer of the semiconductor stack and having a groove exposing the semiconductor stack; a first electrode pad positioned on an n-type compound semiconductor layer of the semiconductor stack; an electrode extension extending from the first electrode pad and positioned over the groove region; and an upper insulating layer interposed between the first electrode pad and the semiconductor stack. In addition, the n-type compound semiconductor layer includes an n-type contact layer, and the n-type contact layer has a Si doping concentration of 5 to 7×1018/cm3 and a thickness in the range of 5 to 10 um.

Abstract translation: 本文公开了一种高效率发光二极管。 发光二极管包括：位于支撑衬底上的半导体堆叠; 反射金属层，位于所述支撑基板和所述半导体堆叠之间，以与所述半导体堆叠的p型化合物半导体层欧姆接触并具有暴露所述半导体叠层的沟槽; 位于所述半导体叠层的n型化合物半导体层上的第一电极焊盘; 电极延伸部，其从所述第一电极焊盘延伸并定位在所述沟槽区域上; 以及介于所述第一电极焊盘和所述半导体堆叠之间的上绝缘层。 此外，n型化合物半导体层包括n型接触层，n型接触层的Si掺杂浓度为5〜7×1018 / cm3，厚度为5〜10μm。

公开(公告)号：US20150137216A1

公开(公告)日：2015-05-21

申请号：US14534181

申请日：2014-11-06

Applicant: Seok-Won LEE ,  Joon-Hee LEE ,  Dong-Seog EUN ,  Chang-Hyun LEE

Inventor： Seok-Won LEE ,  Joon-Hee LEE ,  Dong-Seog EUN ,  Chang-Hyun LEE

IPC: H01L27/115 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

Abstract translation: 垂直存储器件包括衬底，通道，栅极线和连接部分。 多个通道在与基板的顶表面垂直的第一方向上延伸。 多个栅极线在第一方向上被堆叠以彼此间隔开并且在第二长度方向上延伸，每个栅极线与通道组的每组通道的每个通道的外侧壁相交。 栅极线形成包括多个垂直电平的阶梯结构。 连接部分连接位于相同垂直高度的多条栅极线的一组栅极线，该连接部分从栅极线组的栅极线延伸的第二方向发散。

公开(公告)号：US08937327B2

公开(公告)日：2015-01-20

申请号：US13202210

申请日：2010-03-24

Applicant: Won Cheol Seo ,  Dae Sung Kal ,  Joon Hee Lee ,  Chang Youn Kim

Inventor： Won Cheol Seo ,  Dae Sung Kal ,  Joon Hee Lee ,  Chang Youn Kim

IPC: H01L33/00 ,  H01L25/075 ,  H01L27/15 ,  H01L33/38 ,  H01L33/40 ,  H01L33/64

CPC classification number: H01L25/0753 ,  H01L27/153 ,  H01L33/0079 ,  H01L33/38 ,  H01L33/405 ,  H01L33/641 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2933/0016

Abstract: A light emitting device having a plurality of light emitting cells is disclosed. The light emitting device comprises a substrate; a plurality of light emitting cells positioned on the substrate to be spaced apart from one another, each of the light emitting cells comprising a p-type lower semiconductor layer, an active layer and an n-type upper semiconductor layer; p-electrodes positioned to be spaced apart from one another between the substrate and the light emitting cells, the respective p-electrodes being electrically connected to the corresponding lower semiconductor layers, each of the p-electrodes having an extension extending toward adjacent one of the light emitting cells; n-electrodes disposed on upper surfaces of the respective light emitting cells, wherein a contact surface of each of the n-electrodes electrically contacting with each light emitting cell exists both sides of any straight line that bisects the light emitting cell across the center of the upper surface of the light emitting cell; a side insulating layer for covering sides of the light emitting cells; and wires for connecting the p-electrodes and the n-electrodes, the wires being spaced apart from the sides of the light emitting cells by the side insulating layer.

Abstract translation: 公开了一种具有多个发光单元的发光器件。 发光器件包括衬底; 位于所述基板上的多个发光单元彼此间隔开，每个所述发光单元包括p型下半导体层，有源层和n型上半导体层; p电极被定位成在衬底和发光单元之间彼此间隔开，各个p电极电连接到相应的下半导体层，每个p电极具有延伸到相邻的一个 发光单元; 设置在各个发光单元的上表面上的n电极，其中与每个发光单元电接触的每个n电极的接触表面存在于将所述发光单元平分在所述发光单元的中心的任何直线的两侧 发光单元的上表面; 用于覆盖所述发光单元的侧面的侧绝缘层; 以及用于连接p电极和n电极的电线，电线通过侧绝缘层与发光单元的侧面间隔开。

公开(公告)号：US20120318567A1

公开(公告)日：2012-12-20

申请号：US13495216

申请日：2012-06-13

Applicant: Jong-Hyun PARK ,  Jee-Yong KIM ,  Joon-Hee LEE ,  Jai-Hyuk SONG ,  Sang-Youn JO

Inventor： Jong-Hyun PARK ,  Jee-Yong KIM ,  Joon-Hee LEE ,  Jai-Hyuk SONG ,  Sang-Youn JO

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/09

CPC classification number: H01L23/522 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wiring structure includes a first plug extending through a first insulating interlayer on a substrate, a first wiring extending through a second insulating interlayer on the first insulating interlayer and the first wiring is electrically connected to the first plug, a diffusion barrier layer pattern on the first wiring and on the second insulating interlayer, a portion of the second insulating interlayer being free of being covered by the diffusion barrier layer pattern, a second plug extending through the diffusion barrier layer pattern, the second plug is in contact with the first wiring, and a second wiring electrically connected to the second plug.

Abstract translation: 布线结构包括延伸穿过基板上的第一绝缘夹层的第一插塞，延伸穿过第一绝缘夹层上的第二绝缘夹层的第一布线和第一布线电连接到第一插头，扩散阻挡层图案 第一布线并且在第二绝缘中间层上，第二绝缘中间层的一部分不被扩散阻挡层图案覆盖，延伸穿过扩散阻挡层图案的第二插塞，第二插塞与第一布线接触， 以及电连接到第二插头的第二布线。

公开(公告)号：US20120160817A1

公开(公告)日：2012-06-28

申请号：US13410884

申请日：2012-03-02

Applicant: Chang Youn KIM ,  Joon Hee LEE ,  Jong Kyun YOU ,  Hwa Mok KIM

Inventor： Chang Youn KIM ,  Joon Hee LEE ,  Jong Kyun YOU ,  Hwa Mok KIM

IPC: B23K26/38

CPC classification number: H01L33/0079

Abstract: An approach is provided for fabricating a light emitting diode using a laser lift-off apparatus. The approach includes growing an epitaxial layer including a first conductive-type compound semiconductor layer, an active layer and a second conductive-type compound semiconductor layer on a first substrate, bonding a second substrate, having a different thermal expansion coefficient from that of the first substrate, to the epitaxial layers at a first temperature of the first substrate higher than a room temperature, and separating the first substrate from the epitaxial layer by irradiating a laser beam through the first substrate at a second temperature of the first substrate higher than the room temperature but not more than the first temperature.

Abstract translation: 提供了一种使用激光剥离装置制造发光二极管的方法。 该方法包括在第一衬底上生长包括第一导电型化合物半导体层，有源层和第二导电型化合物半导体层的外延层，将具有不同于第一衬底的热膨胀系数不同的第二衬底 衬底，在第一衬底的高于室温的第一温度下到外延层，并且通过在第一衬底的高于室的第二温度下照射穿过第一衬底的激光束将第一衬底与外延层分离 温度不高于第一温度。

公开(公告)号：US20120007109A1

公开(公告)日：2012-01-12

申请号：US13237778

申请日：2011-09-20

Applicant: Won Cheol SEO ,  Joon Hee LEE ,  Jong Kyun YOU ,  Chang Youn KIM ,  Jin Cheul SHIN ,  Hwa Mok KIM ,  Jang Woo LEE ,  Yeo Jin YOON ,  Jong Kyu KIM

Inventor： Won Cheol SEO ,  Joon Hee LEE ,  Jong Kyun YOU ,  Chang Youn KIM ,  Jin Cheul SHIN ,  Hwa Mok KIM ,  Jang Woo LEE ,  Yeo Jin YOON ,  Jong Kyu KIM

IPC: H01L33/08 ,  H01L33/36

CPC classification number: H01L33/60 ,  H01L25/0753 ,  H01L27/156 ,  H01L33/007 ,  H01L33/0079 ,  H01L33/06 ,  H01L33/22 ,  H01L33/32 ,  H01L33/46 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2933/0058 ,  H01L2933/0066 ,  H01L2924/00

Abstract: Disclosed are a light emitting device and a method of fabricating the same. The light emitting device comprises a substrate. A plurality of light emitting cells are disposed on top of the substrate to be spaced apart from one another. Each of the light emitting cells comprises a first upper semiconductor layer, an active layer, and a second lower semiconductor layer. Reflective metal layers are positioned between the substrate and the light emitting cells. The reflective metal layers are prevented from being exposed to the outside.

Abstract translation: 公开了一种发光器件及其制造方法。 发光器件包括衬底。 多个发光单元设置在基板的顶部上以彼此间隔开。 每个发光单元包括第一上半导体层，有源层和第二下半导体层。 反射金属层位于基板和发光单元之间。 防止反射金属层暴露于外部。

公开(公告)号：US20110316026A1

公开(公告)日：2011-12-29

申请号：US13099127

申请日：2011-05-02

Applicant: Chang Youn KIM ,  Joon Hee LEE ,  Jong Kyun YOU ,  Hong Chol LIM ,  Hwa Mok KIM

Inventor： Chang Youn KIM ,  Joon Hee LEE ,  Jong Kyun YOU ,  Hong Chol LIM ,  Hwa Mok KIM

IPC: H01L33/10

CPC classification number: H01L33/10 ,  H01L33/025 ,  H01L2933/0091

Abstract: An exemplary embodiment of the present invention relates to a light emitting diode (LED) including a substrate, a first nitride semiconductor layer arranged on the substrate, an active layer arranged on the first nitride semiconductor layer, a second nitride semiconductor layer arranged on the active layer, a third nitride semiconductor layer disposed between the first nitride semiconductor layer or between the second nitride semiconductor layer and the active layer, the third nitride semiconductor layer comprising a plurality of scatter elements within the third nitride semiconductor layer, and a distributed Bragg reflector (DBR) comprising a multi-layered structure, the substrate being arranged between the DBR and the third nitride semiconductor layer.

Abstract translation: 本发明的示例性实施例涉及一种发光二极管（LED），其包括衬底，布置在衬底上的第一氮化物半导体层，布置在第一氮化物半导体层上的有源层，布置在有源层上的第二氮化物半导体层 层，设置在第一氮化物半导体层之间或第二氮化物半导体层和有源层之间的第三氮化物半导体层，在第三氮化物半导体层内包括多个散射元件的第三氮化物半导体层和分布式布拉格反射器 DBR），所述基板布置在所述DBR和所述第三氮化物半导体层之间。