Multilayer ceramic electronic component
    1.
    发明授权
    Multilayer ceramic electronic component 有权
    多层陶瓷电子元件

    公开(公告)号:US08437115B2

    公开(公告)日:2013-05-07

    申请号:US13478900

    申请日:2012-05-23

    IPC分类号: H01G4/06 H01G4/008

    CPC分类号: H01G4/30 H01G4/012 H01G4/1209

    摘要: There is provided a multilayer ceramic electronic component, including: a ceramic body including a dielectric layer having an average thickness of 0.6 μm or less; and first and second inner electrode layers within the ceramic body, disposed to face each other with the dielectric layer interposed therebetween, wherein the dielectric layer includes contact dielectric grains in contact with the first or second inner electrode layer and non-contact dielectric grains not in contact with the first or second inner electrode layer, and, when an average thickness of the dielectric layer is defined as td and an average diameter of the contact dielectric grains is defined as De, De/td≦0.35 is satisfied. The multilayer ceramic electronic component has improved continuity of the inner electrode layer, large capacitance, extended accelerated lifespan and excellent reliability.

    摘要翻译: 提供了一种多层陶瓷电子部件,其包括:陶瓷体,其包括平均厚度为0.6μm以下的电介质层; 以及陶瓷体内的第一和第二内部电极层,被设置为彼此相对地插入介电层,其中介电层包括与第一或第二内部电极层接触的接触电介质晶粒和不在 与第一或第二内部电极层接触,并且当电介质层的平均厚度被定义为td,并且接触介电晶粒的平均直径被定义为De时,满足De/td@0.35。 多层陶瓷电子部件具有改善的内部电极层的连续性,大的电容,延长的加速寿命和优异的可靠性。

    MULTILAYER CERAMIC ELECTRONIC COMPONENT
    2.
    发明申请
    MULTILAYER CERAMIC ELECTRONIC COMPONENT 有权
    多层陶瓷电子元件

    公开(公告)号:US20130027842A1

    公开(公告)日:2013-01-31

    申请号:US13478900

    申请日:2012-05-23

    IPC分类号: H01G4/12

    CPC分类号: H01G4/30 H01G4/012 H01G4/1209

    摘要: There is provided a multilayer ceramic electronic component, including: a ceramic body including a dielectric layer having an average thickness of 0.6 μm or less; and first and second inner electrode layers within the ceramic body, disposed to face each other with the dielectric layer interposed therebetween, wherein the dielectric layer includes contact dielectric grains in contact with the first or second inner electrode layer and non-contact dielectric grains not in contact with the first or second inner electrode layer, and, when an average thickness of the dielectric layer is defined as td and an average diameter of the contact dielectric grains is defined as De, De/td≦0.35 is satisfied. The multilayer ceramic electronic component has improved continuity of the inner electrode layer, large capacitance, extended accelerated lifespan and excellent reliability.

    摘要翻译: 提供了一种多层陶瓷电子部件,其包括:陶瓷体,其包括平均厚度为0.6μm以下的电介质层; 以及陶瓷体内的第一和第二内部电极层,被设置为彼此相对地插入介电层,其中介电层包括与第一或第二内部电极层接触的接触电介质晶粒和不在 与第一或第二内部电极层接触,并且当电介质层的平均厚度被定义为td并且接触电介质晶粒的平均直径被定义为De时,满足De / td≦̸ 0.35。 多层陶瓷电子部件具有改善的内部电极层的连续性,大的电容,延长的加速寿命和优异的可靠性。

    Tributary unit signal cross-connection apparatus
    3.
    发明授权
    Tributary unit signal cross-connection apparatus 失效
    支路单元信号交叉连接装置

    公开(公告)号:US5914952A

    公开(公告)日:1999-06-22

    申请号:US758257

    申请日:1996-11-27

    CPC分类号: H04L49/101 H04J2203/0007

    摘要: A cross-connection apparatus for tributary unit-12 signal included in a synchronous transfer module-N signal used as a connection signal between synchronous digital hierarchy network nodes, is provided, including, an input/output and tributary unit time switching means for receiving a signal structured in the form of a frame (HEBUS) made up with an administration unit 3 signal, identifier byte and bit interleaved parity byte, performing an administration unit 3 pointer processing, virtual container 3 path overhead processing and tributary unit-12 pointer processing in order to be connected to the switching network, and thus performing a tributary unit-12 unit switching function; and a space switching means for receiving a frame (LBUS) made up with the tributary unit-12 signal, identifier byte and bit interleaved parity byte, namely, an LBUS signal, from the input/output and tributary unit time switching means, the means performing and outputting a space switching operation with the signal.

    摘要翻译: 提供了包括在用作同步数字分层网络节点之间的连接信号的同步传输模块-N信号中的支流单元12信号的交叉连接装置,包括:输入/输出和支路单元时间切换装置, 由管理单元3信号,标识符字节和比特交织奇偶校验字节构成的帧(HEBUS)形式的信号,执行管理单元3指针处理,虚拟容器3路径开销处理和支持单元12指针处理 顺序连接到交换网络,从而执行支路单元12单元切换功能; 以及空间切换装置,用于从输入/输出和支路单元时间切换装置接收由辅助单元12信号,标识符字节和比特交织的奇偶校验字节(即LBUS信号)构成的帧(LBUS),该装置 执行并输出具有该信号的空间切换操作。

    Multilayer ceramic capacitor
    4.
    发明授权
    Multilayer ceramic capacitor 有权
    多层陶瓷电容器

    公开(公告)号:US08559160B2

    公开(公告)日:2013-10-15

    申请号:US13479012

    申请日:2012-05-23

    IPC分类号: H01G4/005 H01G4/06

    摘要: There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t1/td) of a width t1 of the offset portion to a thickness td of the dielectric layer is 1 to 10.

    摘要翻译: 提供了多层陶瓷电容器。 电容器包括:具有电介质层的多层体; 以及设置在所述多层体中的第一和第二内部电极,所述电介质层设置在所述第一和第二内部电极之间,其中,在所述多层体的宽度方向截取的截面中,将偏移部分定义为 相邻的第一和第二内部电极彼此不重叠的部分,并且偏移部分的宽度t1与电介质层的厚度td的比率(t1 / td)为1〜10。

    MULTILAYER CERAMIC CAPACITOR
    5.
    发明申请
    MULTILAYER CERAMIC CAPACITOR 有权
    多层陶瓷电容器

    公开(公告)号:US20120307418A1

    公开(公告)日:2012-12-06

    申请号:US13479012

    申请日:2012-05-23

    IPC分类号: H01G4/12

    摘要: There is provided a multilayer ceramic capacitor. The capacitor includes: a multilayer body having a dielectric layer; and first and second internal electrodes disposed in the multilayer body, the dielectric layer being disposed between the first and second internal electrodes, wherein, in a cross-section taken in a width-thickness direction of the multilayer body, an offset portion is defined as a portion where adjacent first and second internal electrodes do not overlap with each other, and a ratio (t1/td) of a width t1 of the offset portion to a thickness td of the dielectric layer is 1 to 10.

    摘要翻译: 提供了多层陶瓷电容器。 电容器包括:具有电介质层的多层体; 以及设置在所述多层体中的第一和第二内部电极,所述电介质层设置在所述第一和第二内部电极之间,其中,在所述多层体的宽度方向截取的截面中,将偏移部分定义为 相邻的第一和第二内部电极彼此不重叠的部分,并且偏移部分的宽度t1与电介质层的厚度td的比率(t1 / td)为1〜10。

    Circuit for searching fault location in a device having a plurality of
application specific integrated circuits
    6.
    发明授权
    Circuit for searching fault location in a device having a plurality of application specific integrated circuits 失效
    用于搜索具有多个专用集成电路的设备中的故障位置的电路

    公开(公告)号:US5696788A

    公开(公告)日:1997-12-09

    申请号:US758004

    申请日:1996-11-27

    摘要: The present invention relates to a circuit for searching a fault location in a device having a number of ASIC's, including a first BIP(Bit Interleaved Parity) generating unit, which is coupled to the input stage of the ASIC where a fault will be detected, for calculating and outputting BIP for the specific byte, which is one of overhead bytes that were already utilized, i.e., not in use in transmission line, during a certain period; a BIP extraction unit, which is in parallel connected with the first BIP generating unit, for extracting the same byte as said specific byte from overhead bytes, which are generated and inserted in the previous-stage ASIC, in order to compare with BIP inputted into the first BIP generating unit during a certain period; a BIP comparison unit for simply comparing the result outputted from the first BIP generating unit with the result outputted from the BIP extraction unit; a BIP accumulation unit for accumulating the results outputted by the BIP comparison unit; a BIP threshold interrupt processing unit for comparing the results accumulated by the BIP accumulation unit with the threshold value which is used as the reference for generating an interrrupt, and then externally outputting the compared result; a second BIP generating unit, which is coupled to the output stage of the ASIC, for calculating and then outputting BIP for all the bytes within the transmission line(HBUS) during a certain period in order to inspect the signal of HBUS to the next-stage ASIC; and a BIP inserting unit for inserting the result generated from the second BIP generating unit into the specific byte location whithin said transmission line.

    摘要翻译: 本发明涉及一种用于搜索具有多个ASIC的设备中的故障位置的电路​​,该电路包括第一BIP(位交错奇偶校验)产生单元,该第一BIP(位交错奇偶校验)产生单元耦合到将检测故障的ASIC的输入级, 用于计算和输出特定字节的BIP,该特定字节是在一段时间内已经使用的开销字节之一,即在传输线中不使用的; BIP提取单元,其与第一BIP生成单元并联连接,用于从生成并插入前一级ASIC的开销字节中提取与所述特定字节相同的字节,以便与输入到 在一段时间内第一个BIP生成单元; BIP比较单元,用于简单地将从第一BIP产生单元输出的结果与从BIP提取单元输出的结果进行比较; BIP累加单元,用于累加由BIP比较单元输出的结果; BIP阈值中断处理单元,用于将由BIP累积单元累积的结果与用作产生中断的基准的阈值进行比较,然后从外部输出比较结果; 第二BIP生成单元,其耦合到ASIC的输出级,用于计算然后在一定时间段期间输出传输线(HBUS)内的所有字节的BIP,以便检查HBUS到下一代的信号。 阶段ASIC; 以及BIP插入单元,用于将从第二BIP生成单元生成的结果插入到所述传输线中的特定字节位置。

    Synchronous digital hierarchy digital cross-connection apparatus
    8.
    发明授权
    Synchronous digital hierarchy digital cross-connection apparatus 失效
    同步数字分层数字交叉连接装置

    公开(公告)号:US5917818A

    公开(公告)日:1999-06-29

    申请号:US761499

    申请日:1996-12-06

    摘要: A synchronous digital hierarchy digital cross-connection apparatus. The apparatus includes a synchronous signal connecting unit having a STM-N signal receiving part, a reversely multiplexing part and a STM-N signal transmitting part; an AU frame phase arranging and signal supervising unit; and an AU switching unit. The AU frame phase arranging and signal supervising unit includes a downward signal inputting part, and AU frame aligner, a signal path supervisor, a downward signal outputting part, and upward signal inputting part, an unconnected signal supervising and generating part, a selector, an upward signal outputting part and a CPU interface.

    摘要翻译: 一种同步数字分层数字交叉连接装置。 该装置包括具有STM-N信号接收部分,反向复用部分和STM-N信号发送部分的同步信号连接单元; 一个AU帧相位排列和信号监控单元; 和AU切换单元。 AU帧相位布置和信号监控单元包括下行信号输入部分和AU帧对准器,信号路径监控器,向下信号输出部分和向上信号输入部分,未连接的信号监控和生成部分,选择器, 向上信号输出部分和CPU接口。