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    Multilayer ceramic capacitor
    1.
    发明授权
    Multilayer ceramic capacitor 有权

    公开(公告)号：US11961673B2

    公开(公告)日：2024-04-16

    申请号：US18133153

    申请日：2023-04-11

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Hwi Dae Kim ,  Ji Hong Jo ,  Woo Chul Shin ,  Sang Soo Park ,  Chan Yoon

    IPC: H01G4/01 ,  H01G4/12

    CPC classification number: H01G4/01 ,  H01G4/1227

    Abstract: A multilayer ceramic electronic component includes a ceramic body comprising dielectric layers and first and second internal electrodes laminatedly disposed in a third direction with respective dielectric layers interposed therebetween, and first electrode and second external electrodes disposed on both surfaces of the ceramic body in the first direction and electrically connected to the first and second internal electrodes. When an absolute value of a horizontal angle in the second direction of the first internal electrode with respect to the first surface of the ceramic body is referred to a first angle of the internal electrode, a total sum of the first angles is less than 10°.

    Multilayer capacitor and board having the same mounted thereon
    2.
    发明授权
    Multilayer capacitor and board having the same mounted thereon 有权

    公开(公告)号：US11869718B2

    公开(公告)日：2024-01-09

    申请号：US17552786

    申请日：2021-12-16

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Gi Sub Lee ,  Ah Young Lee ,  Chung Hyeon Ryu

    IPC: H01G4/248 ,  H01G4/01 ,  H01G4/30 ,  H05K1/18 ,  H05K1/11

    CPC classification number: H01G4/01 ,  H01G4/248 ,  H01G4/30 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/10015

    Abstract: A multilayer capacitor includes a capacitor body having first to sixth surfaces, including a plurality of first and second dielectric layers and a plurality of internal electrodes stacked; and first and second external electrodes. The internal electrode includes first and second internal electrodes, a first floating electrode disposed between the first and second internal electrodes on the first dielectric layer, and second and third floating electrodes disposed on the second dielectric layer. The second floating electrode overlaps a portion of the first internal electrode and a portion of the first floating electrode, and the third floating electrode overlaps a portion of the second internal electrode and a portion of the first floating electrode. a/L is 0.113 or more, in which L is a length of the capacitor body, and a is a distance between the first floating electrode and the first or second internal electrodes.

    Multilayer ceramic capacitor
    4.
    发明授权
    Multilayer ceramic capacitor 有权

    公开(公告)号：US11670451B2

    公开(公告)日：2023-06-06

    申请号：US17675313

    申请日：2022-02-18

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Hwi Dae Kim ,  Ji Hong Jo ,  Woo Chul Shin ,  Sang Soo Park ,  Chan Yoon

    IPC: H01G4/01 ,  H01G4/12

    CPC classification number: H01G4/01 ,  H01G4/1227

    Abstract: A multilayer ceramic electronic component includes a ceramic body comprising dielectric layers and first and second internal electrodes laminated in a third direction with respective dielectric layers interposed therebetween, and first electrode and second external electrodes disposed on both surfaces of the ceramic body in the first direction and electrically connected to the first and second internal electrodes. When an absolute value of a horizontal angle in the second direction of the first internal electrode with respect to the first surface of the ceramic body is referred to a first angle of the internal electrode, a total sum of the first angles is less than 10°.

    CAPACITOR COMPONENT
    5.
    发明申请
    CAPACITOR COMPONENT 审中-公开

    公开(公告)号：US20190237251A1

    公开(公告)日：2019-08-01

    申请号：US16104570

    申请日：2018-08-17

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Chang Soo JANG ,  Ho Phil JUNG ,  Seung Mo LIM ,  Tae Joon PARK

    IPC: H01G4/01 ,  H01G4/008 ,  H01G4/12 ,  H01G4/252

    CPC classification number: H01G4/01 ,  H01G4/008 ,  H01G4/1209 ,  H01G4/252

    Abstract: A capacitor component includes: a semiconductor substrate including first and second portions, a trench penetrating through the substrate from one surface of the substrate to the other surface of the substrate to separate the first and second portions of the substrate from each other, a dielectric layer disposed in the trench and on the one surface of the substrate; a first pad electrode and a second pad electrode spaced apart from each other, and penetrating through the dielectric layer to be in contact with the first and second portions of the substrate, respectively, and a passivation layer disposed on the dielectric layer, covering portions of the first pad electrode and the second pad electrode, and exposing at least a portion of each of the first pad electrode and the second pad electrode.

    FERROELECTRIC MEMORY, DATA READING/WRITING METHOD AND MANUFACTURING METHOD THEREOF AND CAPACITOR STRUCTURE
    6.
    发明申请
    FERROELECTRIC MEMORY, DATA READING/WRITING METHOD AND MANUFACTURING METHOD THEREOF AND CAPACITOR STRUCTURE 审中-公开

    公开(公告)号：US20180366174A1

    公开(公告)日：2018-12-20

    申请号：US15942599

    申请日：2018-04-02

    Applicant: NuStorage Technology Co., Ltd.

    Inventor： FU-CHOU LIU

    IPC: G11C11/22 ,  H01L27/108 ,  H01G4/01 ,  H01G4/08

    CPC classification number: G11C11/221 ,  G11C11/2257 ,  G11C11/2273 ,  G11C11/2275 ,  H01G4/01 ,  H01G4/08 ,  H01L27/10852

    Abstract: A selected ferroelectric memory cell of a ferroelectric memory is electrically connected to a first bit line, a second bit line, a first word line, a second word line and a plate line. The selected ferroelectric memory cell includes a first field effect transistor (“FET”), a second FET and a ferroelectric capacitor. A control terminal and a first access terminal of the first FET are electrically connected to the first word line and the first bit line, respectively. A control terminal and a first access terminal of the second FET are electrically connected to the second word line and the second bit line, respectively. A second access terminal of the first FET is electrically connected to a first capacitor electrode of the ferroelectric capacitor and a second terminal of the second FET. A second capacitor electrode of the ferroelectric capacitor is electrically connected to the plate line.

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