公开(公告)号：US20080113485A1

公开(公告)日：2008-05-15

申请号：US11559410

申请日：2006-11-14

Applicant: Ta-Jen Wang ,  Yuan-Chen Tsai ,  Shih-Jan Tung

Inventor： Ta-Jen Wang ,  Yuan-Chen Tsai ,  Shih-Jan Tung

IPC: H01L21/762

CPC classification number: H01L21/823437 ,  H01L21/28035 ,  H01L21/3212 ,  H01L21/823481 ,  H01L27/1052 ,  H01L29/66545

Abstract: A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area of the substrate and a plurality of second trench isolation structures are simultaneously formed in the dense trenches area of the substrate. A mask layer is formed between the gaps of the first and the second trench isolation structures. A portion of the first trench isolation structures of the sparse trenches area is then removed. Then, the mask layer is removed until the surface of the substrate is exposed. A polysilicon gate layer is formed over the substrate. Finally, a planarization process is performed to remove a portion of the polysilicon gate layer.

Abstract translation: 提供了评价多晶硅栅极层的厚度均匀性的方法。 提供具有密集沟槽区域和稀疏沟槽区域的衬底。 在衬底的稀疏沟槽区域中形成多个第一沟槽隔离结构，并且在衬底的致密沟槽区域中同时形成多个第二沟槽隔离结构。 在第一和第二沟槽隔离结构的间隙之间形成掩模层。 然后去除稀疏沟槽区域的第一沟槽隔离结构的一部分。 然后，去除掩模层，直到基板的表面露出。 在衬底上形成多晶硅栅极层。 最后，执行平坦化处理以去除多晶硅栅极层的一部分。

公开(公告)号：US20090075567A1

公开(公告)日：2009-03-19

申请号：US12022166

申请日：2008-01-30

Applicant: Ta-Jen Wang ,  Shing-I Chen ,  Ching-Chi Liu ,  Shuang-Hsun Chang

Inventor： Ta-Jen Wang ,  Shing-I Chen ,  Ching-Chi Liu ,  Shuang-Hsun Chang

IPC: B24B53/00 ,  B24B53/12 ,  B24B1/00 ,  B24B53/007

CPC classification number: B24B53/017 ,  B24B53/075 ,  B24B53/12

Abstract: A polishing pad conditioner is provided. The polishing pad includes a substrate, at least one surface-conditioning unit, and at least one groove-cleaning unit. The surface-conditioning unit and the groove-cleaning unit are both disposed on a surface of the substrate. In addition, the surface-conditioning unit is integrally formed with the groove-cleaning unit form.

Abstract translation: 提供了抛光垫调节器。 抛光垫包括基底，至少一个表面调节单元和至少一个凹槽清洁单元。 表面调节单元和槽清洁单元都设置在基板的表面上。 此外，表面调节单元与凹槽清洁单元形式一体地形成。

公开(公告)号：US06913516B1

公开(公告)日：2005-07-05

申请号：US10710508

申请日：2004-07-16

Applicant: Ta-Jen Wang ,  Chi-Hao Chuang ,  Cheng-Hsiang Wu

Inventor： Ta-Jen Wang ,  Chi-Hao Chuang ,  Cheng-Hsiang Wu

IPC: B24B37/00 ,  B24B37/30 ,  B24B37/32 ,  B24B53/007 ,  B24B53/017 ,  B24B53/02 ,  H01L21/304 ,  B24B1/00

CPC classification number: B24B53/017 ,  B24B37/042

Abstract: A dummy process and a polishing-pad conditioning process suitable for a chemical mechanical polishing (CMP) is provided. The CMP apparatus includes a polishing head, a polishing table, and a polishing pad. The polishing head includes a protective hood, a base, a retaining ring and a wafer supporting assembly. The wafer is attached to an attaching surface in the wafer receiving recess. Next, the wafer supporting assembly is moved to make the bottom surface of the retaining ring more protrusive than the bottom surface of the wafer such that the wafer does not contact the surface of the polishing pad. Accordingly, the need for a large number of dummy wafers can be effectively avoided.

Abstract translation: 提供了适用于化学机械抛光（CMP）的虚拟工艺和抛光垫调节工艺。 CMP装置包括抛光头，抛光台和抛光垫。 抛光头包括保护罩，基座，保持环和晶片支撑组件。 晶片附接到晶片容纳凹部中的附接表面。 接下来，晶片支撑组件被移动以使保持环的底表面比晶片的底表面更突出，使得晶片不接触抛光垫的表面。 因此，可以有效地避免对大量虚拟晶片的需要。

公开(公告)号：US07435642B2

公开(公告)日：2008-10-14

申请号：US11559410

申请日：2006-11-14

Applicant: Ta-Jen Wang ,  Yuan-Chen Tsai ,  Shih-Jan Tung ,  Matsuo Hiroshi

Inventor： Ta-Jen Wang ,  Yuan-Chen Tsai ,  Shih-Jan Tung ,  Matsuo Hiroshi

IPC: H01L21/8242

CPC classification number: H01L21/823437 ,  H01L21/28035 ,  H01L21/3212 ,  H01L21/823481 ,  H01L27/1052 ,  H01L29/66545

Abstract: A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area of the substrate and a plurality of second trench isolation structures are simultaneously formed in the dense trenches area of the substrate. A mask layer is formed between the gaps of the first and the second trench isolation structures. A portion of the first trench isolation structures of the sparse trenches area is then removed. Then, the mask layer is removed until the surface of the substrate is exposed. A polysilicon gate layer is formed over the substrate. Finally, a planarization process is performed to remove a portion of the polysilicon gate layer.

Abstract translation: 提供了评价多晶硅栅极层的厚度均匀性的方法。 提供具有密集沟槽区域和稀疏沟槽区域的衬底。 在衬底的稀疏沟槽区域中形成多个第一沟槽隔离结构，并且在衬底的致密沟槽区域中同时形成多个第二沟槽隔离结构。 在第一和第二沟槽隔离结构的间隙之间形成掩模层。 然后去除稀疏沟槽区域的第一沟槽隔离结构的一部分。 然后，去除掩模层，直到基板的表面露出。 在衬底上形成多晶硅栅极层。 最后，执行平坦化处理以去除多晶硅栅极层的一部分。