公开(公告)号：US08760921B2

公开(公告)日：2014-06-24

申请号：US13692076

申请日：2012-12-03

申请人： Masayasu Kawase ,  Takaya Suda

发明人： Masayasu Kawase ,  Takaya Suda

IPC分类号： G11C16/06

CPC分类号： G11C16/06 ,  G06F11/1048 ,  G11C16/26 ,  G11C16/3454 ,  G11C16/349

摘要： According to one embodiment, a storage device includes a nonvolatile memory, a controller configured to copy data stored in a first page in a first block to a second page in a second block, and an ECC circuit. The controller reads data from a part of the first page by using an upper limit voltage and lower limit voltage, performs a direct copy operation in the nonvolatile memory without via the ECC circuit if the number of error cells having threshold voltages higher than the lower limit voltage and lower than or equal to the upper limit voltage is less than or equal to a specified value, and performs error correction by using the ECC circuit if the number of error cells exceeds the specified value.

摘要翻译： 根据一个实施例，存储设备包括非易失性存储器，被配置为将存储在第一块中的第一页中的数据复制到第二块中的第二页的控制器和ECC电路。 控制器通过使用上限电压和下限电压从第一页的一部分读取数据，而不经由ECC电路执行直接复制操作，如果具有高于下限的阈值电压的误差单元的数量 电压小于或等于上限电压小于或等于规定值，并且如果误差单元数超过规定值，则使用ECC电路进行纠错。

公开(公告)号：US07707353B2

公开(公告)日：2010-04-27

申请号：US11757053

申请日：2007-06-01

申请人： Takaya Suda

发明人： Takaya Suda

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F11/3476 ,  G06F11/348 ,  G06F11/3485 ,  G06F2212/1036 ,  G06F2212/7211

摘要： An apparatus for estimating a frequency of access to a storage device that includes a flash memory and a controller for controlling the flash memory includes interface. Data is written into the flash memory in units of a page and being erased from the flash memory in units of a block consisting of pages. The interface is supplied with an internal signal transferred between the flash memory and the controller, configured to recognize the internal signal, and outputs the internal signal as an input signal. An erasure sequence detection section outputs a detection signal when address data is followed by an erasure command requesting erasure of data in the block specified by the address data in the input signal. An address holding section holds address data in the internal signal, and outputs held address data as erasure address data when supplied with the detection signal.

摘要翻译： 用于估计对包括闪速存储器和用于控制闪速存储器的控制器的存储设备的访问频率的装置包括接口。 数据以页面为单位写入闪存，并以由页面组成的块为单位从闪存中擦除。 该接口具有在闪存和控制器之间传输的内部信号，用于识别内部信号，并将内部信号作为输入信号输出。 擦除顺序检测部分，当地址数据后面跟随有请求擦除由输入信号中的地址数据指定的块中的数据的擦除命令时，输出检测信号。 地址保持部分保存内部信号中的地址数据，并且当提供检测信号时，将保持的地址数据作为擦除地址数据输出。

公开(公告)号：US07227788B2

公开(公告)日：2007-06-05

申请号：US11408021

申请日：2006-04-21

申请人： Takaya Suda ,  Hiroaki Muraoka

发明人： Takaya Suda ,  Hiroaki Muraoka

IPC分类号： G11C8/00

CPC分类号： G11C16/102 ,  G11C16/16

摘要： A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

摘要翻译： 一种用于管理非易失性半导体存储器的存储器管理装置，其包括多个块，并且允许以一个块为单位擦除数据，所述存储器管理装置包括：设置单元，被配置为响应于设置要被擦除的数据的地址范围 在写入要擦除的数据的块中的擦除命令时，当相对于非易失性半导体存储器发出擦除命令时，以及控制单元被配置为输出初始值数据作为响应于要读取的数据 数据读取命令，当相对于非易失性半导体存储器发出数据读取命令时，然后当由设置单元设置的地址范围中包括响应于数据读取命令要读取的数据的地址范围时。

公开(公告)号：US20060274565A1

公开(公告)日：2006-12-07

申请号：US11277706

申请日：2006-03-28

申请人： Daisaburo Takashima ,  Shuso Fujii ,  Takuya Futatsuyama ,  Takaya Suda ,  Masaki Momodomi

发明人： Daisaburo Takashima ,  Shuso Fujii ,  Takuya Futatsuyama ,  Takaya Suda ,  Masaki Momodomi

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/2022 ,  G06F2212/7201 ,  G11C8/10

摘要： A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.

摘要翻译： 存储系统包括铁电存储器，闪存EEPROM，控制电路和接口电路。 控制电路被配置为控制铁电存储器和闪存EEPROM。 接口电路被配置为从外部通信。 数据通过写入单元编程在闪存EEPROM中，该写入单元比作为擦除单元的块小并且大于作为程序单元的页面。 铁电存储器使用写入单元存储逻辑地址 - 物理地址转换表。

公开(公告)号：US20120144100A1

公开(公告)日：2012-06-07

申请号：US13368693

申请日：2012-02-08

申请人： Takaya SUDA

发明人： Takaya SUDA

IPC分类号： G06F12/02

CPC分类号： G06F12/0246

摘要： A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

摘要翻译： 存储器系统包括非易失性半导体存储器，其包括由n（n为自然数）写入单元区域构成的第一原始块和由多个写入单元区域组成的第一子块。 控制器将具有第一至第（p个自然数小于n）个地址的数据的数据写入第一原始块。 当控制器接收到写入具有第一写地址的数据的请求并且具有第一写地址的数据存在于第一原始块中时，控制器将具有第一至第p地址之一的第一写地址的数据写入第一子块 。

公开(公告)号：US07872922B2

公开(公告)日：2011-01-18

申请号：US11758035

申请日：2007-06-05

申请人： Takaya Suda

发明人： Takaya Suda

IPC分类号： G11C11/34

CPC分类号： G06F12/0246

摘要： A memory system includes a nonvolatile semiconductor memory which includes a first original block composed of n (n being natural number) write unit areas and a first subblock composed of a plurality of write unit areas. A controller writes data having one of first to p-th (p being natural number smaller than n) addresses into the first original block. The controller writes data which has a first write address of one of the first to p-th addresses into the first subblock when the controller receives request to write data having the first write address and data having the first write address exists in the first original block.

摘要翻译： 存储器系统包括非易失性半导体存储器，其包括由n（n为自然数）写入单元区域构成的第一原始块和由多个写入单元区域组成的第一子块。 控制器将具有第一至第（p个自然数小于n）个地址的数据的数据写入第一原始块。 当控制器接收到写入具有第一写地址的数据的请求并且具有第一写地址的数据存在于第一原始块中时，控制器将具有第一至第p地址之一的第一写地址的数据写入第一子块 。

公开(公告)号：US20080195816A1

公开(公告)日：2008-08-14

申请号：US12100437

申请日：2008-04-10

申请人： Takaya Suda

发明人： Takaya Suda

IPC分类号： G06F12/00

CPC分类号： G06K19/07732 ,  G06K19/10

摘要： A system for authenticating a memory card including: a memory card host device including a plural area authentication module which judges whether the memory card has plural storage areas, and an area switching module which switches a storage area subject to access a different storage area from among plural storage areas; a memory card including plural storage areas, at least one internal register which retains a value indicating the number of storage areas, and a controller which transmits the value indicating the number of the storage areas to the memory card host device; and a bus which transmits and receives data between the memory card host device and the memory card.

摘要翻译： 一种用于认证存储卡的系统，包括：存储卡主机设备，包括判断存储卡是否具有多个存储区域的多区域认证模块;以及区域切换模块，用于将存储不同存储区域的存储区域从 多个存储区域; 包括多个存储区域的存储卡，保存指示存储区域数量的值的至少一个内部寄存器，以及将指示存储区域数量的值发送到存储卡主机设备的控制器; 以及在存储卡主机设备和存储卡之间发送和接收数据的总线。

公开(公告)号：US20060282717A1

公开(公告)日：2006-12-14

申请号：US11228290

申请日：2005-09-19

申请人： Takaya Suda

发明人： Takaya Suda

IPC分类号： G01R31/28

CPC分类号： G11C7/1006 ,  G06F11/1068 ,  G11C16/26 ,  G11C2207/104

摘要： A memory device used attach to a host system includes a nonvolatile memory including a plurality of blocks, each of the blocks being a unit for data erasure and including a plurality of pages, each of the pages including a data section which stores first data supplied from the host system, and a redundancy section which stores at least second data used to manage the first data, a detection circuit which generates a first code used to detect a first error contained in the second data, and detects the first error based on the first code, and a correction circuit which generates a second code used to detect and correct a second error contained in the first data and the second data, and detects and corrects the second error based on the second code.

摘要翻译： 使用的连接到主机系统的存储器件包括包括多个块的非易失性存储器，每个块是用于数据擦除的单元，并且包括多个页面，每个页面包括数据部分，其存储从 所述主机系统和至少存储用于管理所述第一数据的第二数据的冗余部分，生成用于检测包含在所述第二数据中的第一错误的第一代码的检测电路，并且基于所述第一数据检测所述第一错误 代码和校正电路，其生成用于检测和校正包含在第一数据和第二数据中的第二错误的第二代码，并且基于第二代码来检测和校正第二错误。

公开(公告)号：US20060274566A1

公开(公告)日：2006-12-07

申请号：US11443388

申请日：2006-05-31

申请人： Daisaburo Takashima ,  Shuso Fujii ,  Takaya Suda ,  Hiroshi Sukegawa

发明人： Daisaburo Takashima ,  Shuso Fujii ,  Takaya Suda ,  Hiroshi Sukegawa

IPC分类号： G11C11/22

CPC分类号： G11C14/00 ,  G06F12/0246 ,  G06F2212/7207 ,  G11C7/1075 ,  G11C11/22 ,  G11C16/0483

摘要： A memory system includes a ferroelectric memory formed by arranging a plurality of memory cells having a ferroelectric capacitor and cell transistor, a flash EEPROM formed by arranging a plurality of memory cells having a floating gate and capable of electrically erasing and writing data, a control circuit configured to control the ferroelectric memory and flash EEPROM, and an interface circuit configured to communicate with the outside. The flash EEPROM stores data. The ferroelectric memory stores at least one of root information for storing the data, directory information, the file name of the data, the file size of the data, file allocation table information storing the storage location of the data, and the write completion time of the data.

摘要翻译： 存储器系统包括通过布置具有铁电电容器和单元晶体管的多个存储单元形成的铁电存储器，通过布置具有浮动栅极并能够电擦除和写入数据的多个存储单元形成的快闪EEPROM，控制电路 被配置为控制铁电存储器和闪存EEPROM，以及被配置为与外部通信的接口电路。 闪存EEPROM存储数据。 铁电存储器存储用于存储数据的根信息，目录信息，数据的文件名，数据的文件大小，存储数据的存储位置的文件分配表信息和写入完成时间中的至少一个 数据。

公开(公告)号：US20060187738A1

公开(公告)日：2006-08-24

申请号：US11408021

申请日：2006-04-21

申请人： Takaya Suda ,  Hiroaki Muraoka

发明人： Takaya Suda ,  Hiroaki Muraoka

IPC分类号： G11C8/00

CPC分类号： G11C16/102 ,  G11C16/16

摘要： A memory management device for managing a nonvolatile semiconductor memory which comprises a plurality of blocks, and permits data to be erased in units of one block, the memory management device comprises a setting unit configured to set an address range of data to be erased in response to an erase command in a block in which the data to be erased is written, when the erase command is issued with respect to the nonvolatile semiconductor memory and a controlling unit configured to output initial-value data as data to be read in response to a data read command, when the data read command is issued with respect to the nonvolatile semiconductor memory, and then when an address range of the data to be read in response to the data read command is included in the address range set by the setting unit.

摘要翻译： 一种用于管理非易失性半导体存储器的存储器管理装置，其包括多个块，并且允许以一个块为单位擦除数据，所述存储器管理装置包括：设置单元，被配置为响应于设置要被擦除的数据的地址范围 在写入要擦除的数据的块中的擦除命令时，当相对于非易失性半导体存储器发出擦除命令时，以及控制单元被配置为输出初始值数据作为响应于要读取的数据 数据读取命令，当相对于非易失性半导体存储器发出数据读取命令时，然后当由设置单元设置的地址范围中包括响应于数据读取命令要读取的数据的地址范围时。