公开(公告)号：US08861582B2

公开(公告)日：2014-10-14

申请号：US13178744

申请日：2011-07-08

申请人： Takayuki Shibasaki

发明人： Takayuki Shibasaki

IPC分类号： H04L27/01 ,  H04L25/03

CPC分类号： H04L25/03057 ,  H04L2025/03503

摘要： A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.

摘要翻译： 判决反馈均衡器包括：L个均衡计算电路，用于对采样第一采样之前的输入数据中采样的第二样本的M个组合中的每一个进行输入数据的第一采样的均衡计算; 第一逻辑电路，用于通过在对所述L个均衡计算电路中的至少一个均衡计算电路计算的M个计算值的计算值基于在对所述第一数据采样之前采样的第三样本的数据判定值进行选择和排列来生成第一M个逻辑值 ; 以及选择电路，用于基于在对所述第三样本进行采样之前采样的第四样本的数据判定值来选择所述第一M个逻辑值中的一个，并将所选择的逻辑值输出作为所述第一样本的数据判定值。

公开(公告)号：US08698528B2

公开(公告)日：2014-04-15

申请号：US13617922

申请日：2012-09-14

申请人： Takayuki Shibasaki

发明人： Takayuki Shibasaki

IPC分类号： H03L7/06

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H04L7/0025

摘要： An apparatus includes an integration circuit that integrates values of one of a data center and a data edge of input data, based on clock signals, a sampling circuit that samples another at the data center and a data edge of the input data, based on clock signals, a first determination circuit that determines a data value of an integration value of the integration circuit, a second determination circuit that determines a data value of a sampling value of the sampling circuit, a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit, and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the clock signals.

摘要翻译： 一种装置包括：积分电路，其基于时钟信号对输入数据的数据中心和数据边缘中的一个的值进行积分，基于时钟的数据中心对其进行采样的采样电路和输入数据的数据沿， 信号，确定积分电路的积分值的数据值的第一确定电路，确定采样电路的采样值的数据值的第二确定电路，检测输入数据的相位信息的相位检测电路 基于由第一确定电路和第二确定电路确定的数据值，以及相位调整电路，其根据相位信息调整参考时钟的相位以跟踪输入数据的相位，因此 作为时钟信号输出。

公开(公告)号：US08494103B2

公开(公告)日：2013-07-23

申请号：US13310773

申请日：2011-12-04

申请人： Takayuki Shibasaki

发明人： Takayuki Shibasaki

IPC分类号： H04L7/00

CPC分类号： H04L25/03885 ,  H04L7/0029 ,  H04L7/0058 ,  H04L25/0232 ,  H04L25/063 ,  H04L2025/0349 ,  H04L2025/03636 ,  H04L2025/03687

摘要： A reception circuit includes: a sampling circuit to sample an input data signal based on a clock signal and output a sampled signal; a data interpolation circuit to interpolate the sampled signal based on phase information corresponding to the sampled signal and output an interpolated data signal; an interpolation error decision circuit to output an interpolation error based on the sampled signal and the phase information; a decision/equalization circuit to equalize the interpolated data signal using an equalization coefficient set based on the interpolation error, to check an equalized interpolated data signal and to output a checked signal; and a phase detection circuit to generate the phase information based on at least one of the checked signal and the equalized interpolated data signal and output the phase information to the data interpolation circuit and the interpolation error decision circuit.

摘要翻译： 接收电路包括：采样电路，用于基于时钟信号对输入数据信号进行采样并输出采样信号; 数据插值电路，用于根据对应于采样信号的相位信息内插采样信号，并输出内插数据信号; 内插误差判定电路，根据取样信号和相位信息输出插值误差; 判定/均衡电路，使用基于内插误差的均衡系数来均衡内插数据信号，以检查均衡的内插数据信号并输出​​检查信号; 以及相位检测电路，用于基于检查信号和均衡内插数据信号中的至少一个生成相位信息，并将相位信息输出到数据插值电路和插值误差判定电路。

公开(公告)号：US08299948B2

公开(公告)日：2012-10-30

申请号：US13023765

申请日：2011-02-09

申请人： Takayuki Shibasaki ,  Masaya Kibune ,  Takuji Yamamoto

发明人： Takayuki Shibasaki ,  Masaya Kibune ,  Takuji Yamamoto

IPC分类号： H03M1/12

CPC分类号： H03L7/091 ,  H03L7/0807 ,  H03L7/0812

摘要： A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

摘要翻译： 接收电路包括：时钟发生电路，用于以一个周期产生多个时钟信号; 过采样电路，用于基于所述多个时钟信号对输入数据进行过采样，并以单位间隔输出多个数字数据采样; 用于检测数字数据的变化点的数据边界确定电路，基于变化点确定单位间隔的数据边界，并输出与数据边界之间的中心数据相对应的数字数据; 以及时钟相位控制电路，用于控制所述多个时钟信号中的至少一个的相位，使得当所述数据边界之间的第二数量的样本大于阈值时，所述多个采样的第一数量变为特定值 。

公开(公告)号：US20120033726A1

公开(公告)日：2012-02-09

申请号：US13178744

申请日：2011-07-08

申请人： Takayuki SHIBASAKI

发明人： Takayuki SHIBASAKI

IPC分类号： H04L27/01 ,  H04L27/00

CPC分类号： H04L25/03057 ,  H04L2025/03503

摘要： A decision feedback equalizer includes: L equalization calculation circuits to perform an equalization calculation of a first sample of input data for each of M combinations of data decision values of a second sample sampled from the input data before sampling the first sample; a first logic circuit to generate first M logical values by selecting and arranging calculation values of M calculation values calculated by at least one equalization calculation circuit among the L equalization calculation circuits based on a data decision value for a third sample sampled before sampling the first data; and a selection circuit to select one of the first M logical values based on a data decision value for a fourth sample sampled before sampling the third sample, and to output the selected logical value as a data decision value of the first sample.

摘要翻译： 判决反馈均衡器包括：L个均衡计算电路，用于对采样第一采样之前的输入数据中采样的第二样本的M个组合中的每一个进行输入数据的第一采样的均衡计算; 第一逻辑电路，用于通过在对所述L个均衡计算电路中的至少一个均衡计算电路计算的M个计算值的计算值基于在对所述第一数据采样之前采样的第三样本的数据判定值进行选择和排列来生成第一M个逻辑值 ; 以及选择电路，用于基于在对所述第三样本进行采样之前采样的第四样本的数据判定值来选择所述第一M个逻辑值中的一个，并将所选择的逻辑值输出作为所述第一样本的数据判定值。

公开(公告)号：US20110006850A1

公开(公告)日：2011-01-13

申请号：US12821610

申请日：2010-06-23

申请人： Takayuki SHIBASAKI ,  Hirotaka TAMURA

发明人： Takayuki SHIBASAKI ,  Hirotaka TAMURA

IPC分类号： H03L7/00 ,  H03B5/12

CPC分类号： H03L7/0805 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03L7/099

摘要： A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.

摘要翻译： 时钟信号分配装置包括多个LC谐振振荡器，每个谐振振荡器以符合第一电感器和第一电容器的值的频率谐振以振荡信号;注入锁定LC谐振振荡器，其以符合 第二电感器和第二电容器，用于振荡与输入时钟信号同步的信号;以及将多个LC谐振振荡器的振荡节点和注入锁定LC谐振振荡器彼此连接的传输线。

公开(公告)号：US20130169328A1

公开(公告)日：2013-07-04

申请号：US13617922

申请日：2012-09-14

申请人： Takayuki Shibasaki

发明人： Takayuki Shibasaki

IPC分类号： H03L7/06

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H04L7/0025

摘要： An apparatus includes an integration circuit that integrates values of one of a data center and a data edge of input data, based on clock signals, a sampling circuit that samples another at the data center and a data edge of the input data, based on clock signals, a first determination circuit that determines a data value of an integration value of the integration circuit, a second determination circuit that determines a data value of a sampling value of the sampling circuit, a phase detection circuit that detects phase information of the input data, based on a data value determined by the first determination circuit and the second determination circuit, and a phase adjusting circuit that adjusts a phase of a reference clock so as to track a phase of the input data, in accordance with the phase information, so as to output as the clock signals.

摘要翻译： 一种装置包括：积分电路，其基于时钟信号对输入数据的数据中心和数据边缘中的一个的值进行积分，基于时钟的数据中心对其进行采样的采样电路和输入数据的数据沿， 信号，确定积分电路的积分值的数据值的第一确定电路，确定采样电路的采样值的数据值的第二确定电路，检测输入数据的相位信息的相位检测电路 基于由第一确定电路和第二确定电路确定的数据值，以及相位调整电路，其根据相位信息调整参考时钟的相位以跟踪输入数据的相位，因此 作为时钟信号输出。

公开(公告)号：US20110221491A1

公开(公告)日：2011-09-15

申请号：US13023765

申请日：2011-02-09

申请人： Takayuki SHIBASAKI ,  Masaya Kibune ,  Takuji Yamamoto

发明人： Takayuki SHIBASAKI ,  Masaya Kibune ,  Takuji Yamamoto

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  H03L7/0807 ,  H03L7/0812

摘要： A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

摘要翻译： 接收电路包括：时钟发生电路，用于以一个周期产生多个时钟信号; 过采样电路，用于基于所述多个时钟信号对输入数据进行过采样，并以单位间隔输出多个数字数据采样; 用于检测数字数据的变化点的数据边界确定电路，基于变化点确定单位间隔的数据边界，并输出与数据边界之间的中心数据相对应的数字数据; 以及时钟相位控制电路，用于控制所述多个时钟信号中的至少一个的相位，使得当所述数据边界之间的第二数量的样本大于阈值时，所述多个采样的第一数量变为特定值 。

公开(公告)号：US08258882B2

公开(公告)日：2012-09-04

申请号：US12821610

申请日：2010-06-23

申请人： Takayuki Shibasaki ,  Hirotaka Tamura

发明人： Takayuki Shibasaki ,  Hirotaka Tamura

IPC分类号： H03B5/12

CPC分类号： H03L7/0805 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1253 ,  H03B5/1265 ,  H03L7/099

摘要： A clock signal distributing device includes a plurality of LC resonant oscillators, each resonating at a frequency conforming to values of a first inductor and a first capacitor to oscillate a signal, an injection locked LC resonant oscillator that resonates at a frequency conforming to values of a second inductor and a second capacitor to oscillate a signal which is synchronous with an input clock signal, and transmission lines that connect oscillation nodes of the plurality of LC resonant oscillators and the injection locked LC resonant oscillator with one another.

摘要翻译： 时钟信号分配装置包括多个LC谐振振荡器，每个谐振振荡器以符合第一电感器和第一电容器的值的频率谐振以振荡信号;注入锁定LC谐振振荡器，其以符合 第二电感器和第二电容器，用于振荡与输入时钟信号同步的信号;以及将多个LC谐振振荡器的振荡节点和注入锁定LC谐振振荡器彼此连接的传输线。

公开(公告)号：US20120140811A1

公开(公告)日：2012-06-07

申请号：US13310773

申请日：2011-12-04

申请人： Takayuki Shibasaki

发明人： Takayuki Shibasaki

IPC分类号： H04L27/01 ,  H03D1/04 ,  H04L7/00

CPC分类号： H04L25/03885 ,  H04L7/0029 ,  H04L7/0058 ,  H04L25/0232 ,  H04L25/063 ,  H04L2025/0349 ,  H04L2025/03636 ,  H04L2025/03687

摘要： A reception circuit includes: a sampling circuit to sample an input data signal based on a clock signal and output a sampled signal; a data interpolation circuit to interpolate the sampled signal based on phase information corresponding to the sampled signal and output an interpolated data signal; an interpolation error decision circuit to output an interpolation error based on the sampled signal and the phase information; a decision/equalization circuit to equalize the interpolated data signal using an equalization coefficient set based on the interpolation error, to check an equalized interpolated data signal and to output a checked signal; and a phase detection circuit to generate the phase information based on at least one of the checked signal and the equalized interpolated data signal and output the phase information to the data interpolation circuit and the interpolation error decision circuit.

摘要翻译： 接收电路包括：采样电路，用于基于时钟信号对输入数据信号进行采样并输出采样信号; 数据插值电路，用于根据对应于采样信号的相位信息内插采样信号，并输出内插数据信号; 内插误差判定电路，根据取样信号和相位信息输出插值误差; 判定/均衡电路，使用基于内插误差的均衡系数来均衡内插的数据信号，以检查均衡的内插数据信号并输出​​检查信号; 以及相位检测电路，用于基于检查信号和均衡内插数据信号中的至少一个生成相位信息，并将相位信息输出到数据插值电路和插值误差判定电路。