公开(公告)号：US20110221491A1

公开(公告)日：2011-09-15

申请号：US13023765

申请日：2011-02-09

申请人： Takayuki SHIBASAKI ,  Masaya Kibune ,  Takuji Yamamoto

发明人： Takayuki SHIBASAKI ,  Masaya Kibune ,  Takuji Yamamoto

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  H03L7/0807 ,  H03L7/0812

摘要： A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

摘要翻译： 接收电路包括：时钟发生电路，用于以一个周期产生多个时钟信号; 过采样电路，用于基于所述多个时钟信号对输入数据进行过采样，并以单位间隔输出多个数字数据采样; 用于检测数字数据的变化点的数据边界确定电路，基于变化点确定单位间隔的数据边界，并输出与数据边界之间的中心数据相对应的数字数据; 以及时钟相位控制电路，用于控制所述多个时钟信号中的至少一个的相位，使得当所述数据边界之间的第二数量的样本大于阈值时，所述多个采样的第一数量变为特定值 。

公开(公告)号：US08299948B2

公开(公告)日：2012-10-30

申请号：US13023765

申请日：2011-02-09

申请人： Takayuki Shibasaki ,  Masaya Kibune ,  Takuji Yamamoto

发明人： Takayuki Shibasaki ,  Masaya Kibune ,  Takuji Yamamoto

IPC分类号： H03M1/12

CPC分类号： H03L7/091 ,  H03L7/0807 ,  H03L7/0812

摘要： A receiving circuit includes: a clock generating circuit to generate a plurality of clock signals in a cycle; an oversampling circuit to oversample input data based on the plurality of clock signals and output a plurality of samples of digital data in a unit interval; a data boundary determining circuit to detect a changing point of the digital data, determine data boundaries of the unit interval based on the changing point, and output digital data corresponding to a central data between the data boundaries; and a clock phase control circuit to control a phase of at least one of the plurality of clock signals so that a first number of the plurality of samples becomes a certain value when a second number of samples between the data boundaries is larger than a threshold value.

摘要翻译： 接收电路包括：时钟发生电路，用于以一个周期产生多个时钟信号; 过采样电路，用于基于所述多个时钟信号对输入数据进行过采样，并以单位间隔输出多个数字数据采样; 用于检测数字数据的变化点的数据边界确定电路，基于变化点确定单位间隔的数据边界，并输出与数据边界之间的中心数据相对应的数字数据; 以及时钟相位控制电路，用于控制所述多个时钟信号中的至少一个的相位，使得当所述数据边界之间的第二数量的样本大于阈值时，所述多个采样的第一数量变为特定值 。

公开(公告)号：US08798568B2

公开(公告)日：2014-08-05

申请号：US12562712

申请日：2009-09-18

申请人： Masaya Kibune

发明人： Masaya Kibune

IPC分类号： H04B1/18

CPC分类号： H04B3/23 ,  H04B3/238 ,  H04L25/0278 ,  H04L25/03343 ,  H04L25/03878

摘要： A signal transmission method suppresses a reflected wave of a transmission signal on a transmission line, by obtaining level and time information related to the reflected wave by computing a correlation between a data pattern of the transmission signal and the reflected wave, and correcting a waveform of the transmission signal based on the level and time information related to the reflected wave.

摘要翻译： 信号发送方法通过计算发送信号的数据模式与反射波之间的相关性，通过获得与反射波相关的电平和时间信息，并且校正波形，抑制传输线上的发送信号的反射波 基于与反射波相关的电平和时间信息的发送信号。

公开(公告)号：US07859300B2

公开(公告)日：2010-12-28

申请号：US12541633

申请日：2009-08-14

申请人： Masaya Kibune

发明人： Masaya Kibune

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/018528 ,  H03K19/0175

摘要： An input and output circuit apparatus includes a signal generating circuit configured to generate a first signal, an input and output circuit configured to receive the first signal from the signal generating circuit and a second signal to generate an output signal responsive to the first signal and the second signal, an operation test circuit having substantially an identical circuit configuration to the input and output circuit, and configured to receive the first signal from the signal generating circuit and a third signal to generate an output signal responsive to the first signal and the third signal, a check circuit configured to generates a check signal indicative of an operating condition of the operation test circuit in response to the output signal of the operation test circuit, and an adjustment circuit configured to adjust the signal generating circuit in response to the check signal output from the check circuit.

摘要翻译： 一种输入和输出电路装置，包括：信号发生电路，被配置为产生第一信号;输入和输出电路，被配置为从信号发生电路接收第一信号;以及第二信号，以响应于第一信号和 第二信号，操作测试电路，其具有与输入和输出电路基本相同的电路配置，并且被配置为从信号发生电路接收第一信号和第三信号，以响应于第一信号和第三信号产生输出信号 检查电路，被配置为响应于所述操作测试电路的输出信号产生指示所述操作测试电路的操作状态的检查信号;以及调整电路，被配置为响应于所述检查信号输出来调整所述信号发生电路 从检查电路。

公开(公告)号：US20100246734A1

公开(公告)日：2010-09-30

申请号：US12730725

申请日：2010-03-24

申请人： Hirotaka TAMURA ,  Masaya Kibune

发明人： Hirotaka TAMURA ,  Masaya Kibune

IPC分类号： H04L27/08 ,  H04L27/00

CPC分类号： H04L7/0331

摘要： A receiver that receives a train of a plurality of symbols representing digital data, includes: an isolated pulse detector that detects whether the digital data includes an isolated pulse in the symbol train, respectively; a phase detector that detects a timing at which the level of the symbols changes; a symbol value converter that converts the symbols into logical values on the basis of the timing detected by the phase detector; and a data selector that selects a logical value of the isolated pulse instead of the logical value converted by the symbol value converter when the isolated pulse detector detects the digital data containing the isolated pulse.

摘要翻译： 一种接收代表数字数据的多个码元的列的接收机，包括：分离的脉冲检测器，分别检测数字数据是否包括符号列中的隔离脉冲; 检测符号的电平变化的定时的相位检测器; 符号值转换器，其基于由相位检测器检测到的定时将符号转换为逻辑值; 以及当隔离脉冲检测器检测到包含隔离脉冲的数字数据时，选择隔离脉冲的逻辑值而不是由符号值转换器转换的逻辑值的数据选择器。

公开(公告)号：US07936296B2

公开(公告)日：2011-05-03

申请号：US12497910

申请日：2009-07-06

申请人： Masaya Kibune ,  Hisakatsu Yamaguchi

发明人： Masaya Kibune ,  Hisakatsu Yamaguchi

IPC分类号： H03M1/12

CPC分类号： H03M1/205 ,  H03M1/108 ,  H03M1/109 ,  H03M1/365

摘要： An AD converter includes a first amplitude circuit, a second amplitude circuit, and a determination circuit. A control signal line controls a first amplitude gain of the first amplitude circuit and a second amplitude gain of the second amplitude circuit.

摘要翻译： AD转换器包括第一幅度电路，第二幅度电路和确定电路。 控制信号线控制第一幅度电路的第一幅度增益和第二幅度电路的第二幅度增益。

公开(公告)号：US20070273413A1

公开(公告)日：2007-11-29

申请号：US11882562

申请日：2007-08-02

申请人： Masaya Kibune

发明人： Masaya Kibune

IPC分类号： H03B1/00

CPC分类号： H03F3/45183 ,  H03F3/45197 ,  H03F3/45475 ,  H03F2203/45138 ,  H03F2203/45458 ,  H03F2203/45461 ,  H03F2203/45466 ,  H03F2203/45506 ,  H03F2203/45652 ,  H03H11/34

摘要： A clock buffer has a band-pass frequency characteristic, in which a pass band of the buffer includes a fundamental frequency of a clock and a gain for attenuating signals, that is, a gain of less than 0 dB is provided at frequencies below the pass band.

摘要翻译： 时钟缓冲器具有带通频率特性，其中缓冲器的通带包括时钟的基频和用于衰减信号的增益，即小于0dB的增益在低于通过的频率处提供 带。

公开(公告)号：US07283601B2

公开(公告)日：2007-10-16

申请号：US10077875

申请日：2002-02-20

申请人： Hirotaka Tamura ,  Masaya Kibune

发明人： Hirotaka Tamura ,  Masaya Kibune

IPC分类号： H03D3/24

CPC分类号： G06F5/06 ,  G06F1/04 ,  H04L7/0012 ,  H04L7/005

摘要： A timing signal generating system has a clock signal generating circuit, a synchronizing circuit, a phase code recognizing circuit, and a calibration circuit. The clock signal generating circuit generates at least one first clock signal upon receipt of at least one reference clock signal by controlling an output phase thereof with a digital code signal. The synchronizing circuit hands over signals between a group of circuits operated by the first clock signal and an internal circuit operated by a second clock signal. The phase code recognizing circuit recognizes a phase code when the phases of the first clock signal and of the second clock signal are in a particular relationship. The calibration circuit calibrates a relationship between a value of the recognized phase code and a phase difference between the first and second clock signals. The synchronizing circuit is controlled by using phase code data calibrated by the calibration circuit.

摘要翻译： 定时信号发生系统具有时钟信号发生电路，同步电路，相位代码识别电路和校准电路。 时钟信号发生电路在接收到至少一个参考时钟信号时，通过用数字代码信号控制其输出相位来产生至少一个第一时钟信号。 同步电路切换由第一时钟信号操作的一组电路与由第二时钟信号操作的内部电路之间的信号。 当第一时钟信号和第二时钟信号的相位处于特定关系时，相位代码识别电路识别相位代码。 校准电路校准识别的相位码的值与第一和第二时钟信号之间的相位差之间的关系。 通过使用由校准电路校准的相位代码数据来控制同步电路。

公开(公告)号：US20050226355A1

公开(公告)日：2005-10-13

申请号：US11050175

申请日：2005-02-04

申请人： Masaya Kibune ,  Hirotaka Tamura

发明人： Masaya Kibune ,  Hirotaka Tamura

IPC分类号： H04L25/03 ,  H04B3/06 ,  H04B3/18 ,  H04L1/00

CPC分类号： H04L25/0328 ,  H04L25/03038

摘要： A receiver circuit has an equalizer that equalizes a received signal propagating through a transmission medium; a data detection circuit that detects an analog output signal of the equalizer at a data sample timing and outputs a digital signal; an intersymbol interference detection circuit that detects an intersymbol interference level from the analog output signal of the equalizer at the data sample timing and from the digital signal of the data detection circuit; and an equalization characteristic control unit that controls the characteristic of the equalizer to minimize the detected intersymbol interference level. The receiver circuit further has a data sample timing control unit in which the data sample timing is controlled to a sample timing at which the difference between the amplitude of the analog output waveform of the equalizer with respect to an impulse and the amplitude of an ideal impulse response waveform is minimal.

摘要翻译： 接收机电路具有均衡器，其均衡通过传输介质传播的接收信号; 数据检测电路，在数据采样定时检测均衡器的模拟输出信号，并输出数字信号; 符号间干扰检测电路，在数据采样定时和数据检测电路的数字信号中，从均衡器的模拟输出信号中检测出符号间干扰电平; 以及均衡特性控制单元，其控制均衡器的特性以使检测到的符号间干扰电平最小化。 接收器电路还具有数据采样定时控制单元，其中数据采样定时被控制到采样定时，在该采样定时处，均衡器的模拟输出波形的相对于脉冲的幅度与理想脉冲的振幅之差 响应波形最小。

公开(公告)号：US08634454B2

公开(公告)日：2014-01-21

申请号：US12826420

申请日：2010-06-29

申请人： Masaya Kibune ,  Hirotaka Tamura

发明人： Masaya Kibune ,  Hirotaka Tamura

IPC分类号： H03K5/159 ,  H04B1/10

CPC分类号： H04L25/03057 ,  H03K5/086 ,  H04L2025/03471 ,  H04L2025/03636 ,  H04L2025/03649 ,  H04L2025/03751

摘要： A receiver circuit includes: an equalization circuit that equalizes a first signal to obtain a second signal, and adjusts a characteristic of an equalization in accordance with an error between the second signal and a third signal; and a first offset adjustment circuit that adjusts an offset of the first signal in accordance with an error signal indicating the error.

摘要翻译： 接收机电路包括：均衡电路，其对第一信号进行均衡以获得第二信号，并根据第二信号和第三信号之间的误差调整均衡的特性; 以及第一偏移调整电路，其根据指示所述误差的误差信号来调整所述第一信号的偏移。