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22 条记录 (耗时 0.016 秒)

    Demodulator, disk drive device, and phase adjustment method
    5.
    发明授权
    Demodulator, disk drive device, and phase adjustment method 失效
    解调器，磁盘驱动器和相位调整方法

    公开(公告)号：US07333408B2

    公开(公告)日：2008-02-19

    申请号：US11045352

    申请日：2005-01-31

    申请人： Tatsushi Sano ,  Mitsuru Okabe ,  Tadaaki Nomoto

    发明人： Tatsushi Sano ,  Mitsuru Okabe ,  Tadaaki Nomoto

    IPC分类号： G11B20/00

    CPC分类号： G11B20/10222 ,  G11B7/0053 ,  G11B20/10361 ,  G11B2220/2537

    摘要： In a demodulation process of a first modulated signal and a second modulated signal, phase adjustment is automatically performed by generating, in response to demodulation results, an optimum phase value of a second internal reference wave for demodulating the second modulated signal. A phase of a second internal reference wave for demodulating the first modulated signal is also adjusted using the optimum phase value for the automatic adjustment.

    摘要翻译： 在第一调制信号和第二调制信号的解调处理中，通过响应于解调结果生成用于解调第二调制信号的第二内部参考波的最佳相位值来自动执行相位调整。 用于解调第一调制信号的第二内部参考波的相位也使用用于自动调整的最佳相位值进行调整。

    PLL CIRCUIT, RECORDING APPARATUS, AND CLOCK-SIGNAL GENERATING METHOD
    7.
    发明申请
    PLL CIRCUIT, RECORDING APPARATUS, AND CLOCK-SIGNAL GENERATING METHOD 失效
    PLL电路，记录装置和时钟信号发生方法

    公开(公告)号：US20090028017A1

    公开(公告)日：2009-01-29

    申请号：US12143207

    申请日：2008-06-20

    申请人： Tatsushi SANO

    发明人： Tatsushi SANO

    IPC分类号： G11B27/10

    CPC分类号： G11B20/1403 ,  G11B7/0045 ,  G11B7/0053 ,  G11B20/10037 ,  G11B2020/1239

    摘要： A phase-locked loop circuit that generates a clock signal synchronized with an input signal with a predetermined frequency, including an oscillator configured to oscillate and generate the clock signal; a converter configured to convert the input signal into a digital signal using the clock signal generated by the oscillator as a sampling clock; a frequency divider configured to divide a frequency of the clock signal generated by the oscillator to generate a comparison clock signal and send the comparison clock signal as a feedback; a normalizer configured to normalize an amplitude value of the digital signal generated by the converter; and an oscillation controller configured to control a phase of the clock signal generated by the oscillator so as to reduce a phase difference between the normalized digital signal generated by the normalizer and the comparison clock signal sent as a feedback by the frequency divider.

    摘要翻译： 一种锁相环电路，其产生与预定频率的输入信号同步的时钟信号，所述时钟信号包括被配置为振荡并产生所述时钟信号的振荡器; 转换器，被配置为使用由振荡器产生的时钟信号作为采样时钟将输入信号转换成数字信号; 分频器，被配置为分频由振荡器产生的时钟信号的频率，以产生比较时钟信号，并将比较时钟信号作为反馈发送; 归一化器，被配置为对由所述转换器产生的数字信号的振幅值进行归一化; 以及振荡控制器，被配置为控制由振荡器产生的时钟信号的相位，以便减小由归一化器产生的归一化数字信号与作为分频器反馈发送的比较时钟信号之间的相位差。

    PLL circuit, recording apparatus, and clock-signal generating method
    9.
    发明授权
    PLL circuit, recording apparatus, and clock-signal generating method 失效
    PLL电路，记录装置和时钟信号生成方法

    公开(公告)号：US08102743B2

    公开(公告)日：2012-01-24

    申请号：US12143207

    申请日：2008-06-20

    申请人： Tatsushi Sano

    发明人： Tatsushi Sano

    IPC分类号： G11B20/14

    CPC分类号： G11B20/1403 ,  G11B7/0045 ,  G11B7/0053 ,  G11B20/10037 ,  G11B2020/1239

    摘要： A phase-locked loop circuit that generates a clock signal synchronized with an input signal with a predetermined frequency, including an oscillator configured to oscillate and generate the clock signal; a converter configured to convert the input signal into a digital signal using the clock signal generated by the oscillator as a sampling clock; a frequency divider configured to divide a frequency of the clock signal generated by the oscillator to generate a comparison clock signal and send the comparison clock signal as a feedback; a normalizer configured to normalize an amplitude value of the digital signal generated by the converter; and an oscillation controller configured to control a phase of the clock signal generated by the oscillator so as to reduce a phase difference between the normalized digital signal generated by the normalizer and the comparison clock signal sent as a feedback by the frequency divider.

    摘要翻译： 一种锁相环电路，其产生与预定频率的输入信号同步的时钟信号，所述时钟信号包括被配置为振荡并产生所述时钟信号的振荡器; 转换器，被配置为使用由振荡器产生的时钟信号作为采样时钟将输入信号转换成数字信号; 分频器，被配置为分频由振荡器产生的时钟信号的频率，以产生比较时钟信号，并将比较时钟信号作为反馈发送; 归一化器，被配置为对由所述转换器产生的数字信号的振幅值进行归一化; 以及振荡控制器，被配置为控制由振荡器产生的时钟信号的相位，以便减小由归一化器产生的归一化数字信号与作为分频器反馈发送的比较时钟信号之间的相位差。

    Disk drive and pre-pit detection method
    10.
    发明授权
    Disk drive and pre-pit detection method 失效
    磁盘驱动器和预坑检测方法

    公开(公告)号：US07496010B2

    公开(公告)日：2009-02-24

    申请号：US10680109

    申请日：2003-10-08

    申请人： Shinji Ohta ,  Tatsushi Sano

    发明人： Shinji Ohta ,  Tatsushi Sano

    IPC分类号： G11B7/00

    CPC分类号： G11B7/24082 ,  G11B7/0053 ,  G11B7/00745 ,  G11B27/24 ,  G11B2220/216 ,  G11B2220/218 ,  G11B2220/2562

    摘要： A push-pull signal is detected from light reflected from a disk-shaped storage medium on which wobbling grooves are formed as recording tracks and address information is recorded by forming pre-pits on lands between adjacent grooves. A fundamental amplitude variation signal indicating the fundamental amplitude variation of the push-pull signal is acquired, and a reference voltage is generated by adding an offset voltage to the fundamental amplitude variation signal. Pre-pits are detected by comparing the push-pull signal with the reference voltage. Because the reference voltage is produced on the basis of the fundamental amplitude variation signal indicating the variation components of the push-pull signal due to the wobbling of grooves and noise, the variation components due to the wobbling and noise are reflected in the reference voltage. Furthermore, the variation components of the push-pull signal corresponding to the pre-pits are also reflected to a properly small extent in the reference voltage.

    摘要翻译： 从形成有摆动槽的盘形存储介质反射的光作为记录轨迹检测推挽信号，并且通过在相邻槽之间的焊盘上形成预凹坑来记录地址信息。 获取表示推挽信号的基本幅度变化的基本幅度变化信号，并通过将偏移电压加到基本幅度变化信号上而生成基准电压。 通过将推挽信号与参考电压进行比较来检测预坑。 因为基于表示由于槽的波动和噪声引起的推挽信号的变化分量的基本幅度变化信号而产生参考电压，所以由于摆动和噪声引起的变化成分被反映在参考电压中。 此外，对应于预凹坑的推挽信号的变化分量也在参考电压中反映到适当的较小程度。