-
1.发明授权公开(公告)号：US06388330B1
公开(公告)日：2002-05-14
申请号：US09776012
申请日：2001-02-01
IPC分类号： H01L2348
CPC分类号： H01L23/5222 , H01L21/76801 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit and method of manufacture therefore is provided having a semiconductor substrate with a semiconductor device with a dielectric layer over the semiconductor substrate. A conductor core fills the opening in the dielectric layer. An etch stop layer with a dielectric constant below 5.5 is formed over the first dielectric layer and conductor core. A second dielectric layer over the etch stop layer has an opening provided to the conductor core. A second conductor core fills the second opening and is connected to the first conductor core.
摘要翻译： 因此，提供了具有半导体衬底和半导体器件的集成电路和制造方法，所述半导体衬底具有半导体衬底上的介电层。 导体芯填充电介质层中的开口。 在第一介电层和导体芯上形成介电常数低于5.5的蚀刻停止层。 蚀刻停止层上的第二电介质层具有提供给导体芯的开口。 第二导体芯填充第二开口并连接到第一导体芯。
-
公开(公告)号：US5888898A
公开(公告)日：1999-03-30
申请号：US956588
申请日：1997-10-23
申请人： Minh V. Ngo , Khanh Q. Tran , Terri J. Kitson , Lu You , Simon S. Chan , Jean Y. Yang
发明人： Minh V. Ngo , Khanh Q. Tran , Terri J. Kitson , Lu You , Simon S. Chan , Jean Y. Yang
IPC分类号： H01L21/314 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/02134 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/02337 , H01L21/316 , H01L21/31612 , H01L21/76801 , H01L21/76826 , H01L21/76828 , H01L23/5226 , H01L23/5329 , H01L2924/0002
摘要： A patterned metal layer is gap filled with HSQ, an oxide formed thereon by PECVD, e.g., silicon dioxide derived from silane and N.sub.2 O, and planarized. The dielectric constant of the HSQ layer is minimized by baking the deposited HSQ layer in an inert atmosphere, e.g., N.sub.2, before heat soaking in an N.sub.2 O-containing atmosphere for no more than about 10 seconds and subsequent PECVD.
摘要翻译： 图案化的金属层是间隙填充有HSQ，其是通过PECVD在其上形成的氧化物，例如来自硅烷和N 2 O的二氧化硅，并且被平坦化。 通过在惰性气氛例如N 2中烘烤沉积的HSQ层，在含N2O的气氛中热浸泡不超过约10秒并随后的PECVD之后，使HSQ层的介电常数最小化。
-
搜索结果
2 条记录 (耗时 0.009 秒)
