公开(公告)号：US5888898A

公开(公告)日：1999-03-30

申请号：US956588

申请日：1997-10-23

申请人： Minh V. Ngo ,  Khanh Q. Tran ,  Terri J. Kitson ,  Lu You ,  Simon S. Chan ,  Jean Y. Yang

发明人： Minh V. Ngo ,  Khanh Q. Tran ,  Terri J. Kitson ,  Lu You ,  Simon S. Chan ,  Jean Y. Yang

IPC分类号： H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC分类号： H01L21/02134 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02337 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76826 ,  H01L21/76828 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

摘要： A patterned metal layer is gap filled with HSQ, an oxide formed thereon by PECVD, e.g., silicon dioxide derived from silane and N.sub.2 O, and planarized. The dielectric constant of the HSQ layer is minimized by baking the deposited HSQ layer in an inert atmosphere, e.g., N.sub.2, before heat soaking in an N.sub.2 O-containing atmosphere for no more than about 10 seconds and subsequent PECVD.

摘要翻译： 图案化的金属层是间隙填充有HSQ，其是通过PECVD在其上形成的氧化物，例如来自硅烷和N 2 O的二氧化硅，并且被平坦化。 通过在惰性气氛例如N 2中烘烤沉积的HSQ层，在含N2O的气氛中热浸泡不超过约10秒并随后的PECVD之后，使HSQ层的介电常数最小化。

公开(公告)号：US5888911A

公开(公告)日：1999-03-30

申请号：US956590

申请日：1997-10-23

申请人： Minh V. Ngo ,  Khanh Q. Tran ,  Lu You ,  Jean Y. Yang ,  Richard J. Huang

发明人： Minh V. Ngo ,  Khanh Q. Tran ,  Lu You ,  Jean Y. Yang ,  Richard J. Huang

IPC分类号： H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/02164 ,  H01L21/02134 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/02337 ,  H01L21/31051 ,  H01L21/316 ,  H01L21/31612 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

摘要： Patterned metal layers are gap filled with HSQ and heat soaked in an oxidizing environment prior to oxide deposition by PECVD and planarization. Heat soaking is confined to less than about 10 seconds to minimize the dielectric constant of the HSQ layer.

摘要翻译： 图案化的金属层是填充有HSQ的间隙，并且在氧化物沉积之前通过PECVD和平坦化浸泡在氧化环境中的热量。 热浸泡被限制在小于约10秒钟以使HSQ层的介电常数最小化。

公开(公告)号：US06259115B1

公开(公告)日：2001-07-10

申请号：US09262214

申请日：1999-03-04

申请人： Lu You ,  Simon S. Chan ,  Kai Yang

发明人： Lu You ,  Simon S. Chan ,  Kai Yang

IPC分类号： H01L2156

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/76819

摘要： A method is provided for inserting dummy conductive channels along with the interconnected conductive channels. The dummy channels have an approximately even metal weight distribution to provide better plating uniformity, minimize CMP dishing, improve process heating uniformity, improve spin-on process properties, and increase etch and lithography uniformity.

摘要翻译： 提供了一种用于将伪导电通道与互连的导电通道一起插入的方法。 虚拟通道具有大致均匀的金属重量分布，以提供更好的电镀均匀性，使CMP凹陷最小化，改善工艺加热均匀性，提高旋涂工艺性能，并增加蚀刻和光刻均匀性。

公开(公告)号：US5760480A

公开(公告)日：1998-06-02

申请号：US530658

申请日：1995-09-20

申请人： Lu You ,  Robin W. Cheung ,  Simon S. Chan ,  Richard J. Huang

发明人： Lu You ,  Robin W. Cheung ,  Simon S. Chan ,  Richard J. Huang

IPC分类号： H01L21/3205 ,  H01L21/312 ,  H01L21/768 ,  H01L23/31 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  B29B13/00 ,  B05D3/02 ,  H01L21/283

CPC分类号： H01L23/3142 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044

摘要： A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.

公开(公告)号：US5861677A

公开(公告)日：1999-01-19

申请号：US890905

申请日：1997-07-10

申请人： Lu You ,  Robin W. Cheung ,  Simon S. Chan ,  Richard J. Huang

发明人： Lu You ,  Robin W. Cheung ,  Simon S. Chan ,  Richard J. Huang

IPC分类号： H01L21/3205 ,  H01L21/312 ,  H01L21/768 ,  H01L23/31 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  B29B13/00 ,  B05D3/02 ,  H01L21/283

CPC分类号： H01L23/3142 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044

摘要： A low RC delay interconnection pattern is formed with a low resistivity metal, such as copper, and a low dielectric constant material, such as organic polymers. An intermediate bonding layer is formed between the low resistivity metal and low dielectric constant material employing an adhesion promoter, such as a silane-based adhesion promoter. The adhesion promoter can be applied between the metal and dielectric layers or incorporated in the dielectric layer.

摘要翻译： 低阻抗延迟互连图案由诸如铜的低电阻率金属和诸如有机聚合物的低介电常数材料形成。 在使用粘合促进剂的低电阻率金属和低介电常数材料之间形成中间粘合层，例如硅烷类粘合促进剂。 粘合促进剂可以施加在金属和电介质层之间或并入电介质层中。

公开(公告)号：US06200913B1

公开(公告)日：2001-03-13

申请号：US09191040

申请日：1998-11-12

申请人： Lu You ,  Simon S. Chan ,  John Iacoponi ,  Richard J. Huang ,  Robin Cheung

发明人： Lu You ,  Simon S. Chan ,  John Iacoponi ,  Richard J. Huang ,  Robin Cheung

IPC分类号： H01L21324

CPC分类号： H01L21/02134 ,  H01L21/02282 ,  H01L21/31058 ,  H01L21/3124

摘要： This invention comprises improvements in the ways in which spin-on dielectric layers are cured. A semiconductor wafer is coated with a precursor for a spin-on dielectric material, and after the solution is thinned and evened, the wafer is placed in a curing oven, optionally containing an inert gas, and pre-heated to a temperature below which excessive thermomechanical stresses and/or oxidation are not created in the semiconductor wafer. The temperature within the curing oven is then raised to a curing temperature, and thereafter the temperature is slowly lowered to prevent the formation of stress cracks and the loss of dielectric function of the thin film. The curing method of this invention is useful for the manufacture of semiconductor devices employing a variety of spin-on materials.

摘要翻译： 本发明包括改进旋涂电介质层固化的方式。 半导体晶片被涂覆有用于旋涂电介质材料的前体，并且在溶液变薄并均匀之后，将晶片放置在固化炉中，任选地包含惰性气体，并预热到低于该温度的温度 在半导体晶片中不产生热机械应力和/或氧化。 然后将固化炉内的温度升高至固化温度，然后缓慢降低温度，以防止形成应力裂纹和薄膜的介电功能的损失。 本发明的固化方法可用于制造采用各种旋涂材料的半导体器件。

公开(公告)号：US6093635A

公开(公告)日：2000-07-25

申请号：US993124

申请日：1997-12-18

申请人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

发明人： Khanh Tran ,  Richard J. Huang ,  Simon S. Chan ,  Lu You

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC分类号： H01L21/3105 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76828 ,  Y10S438/958

摘要： Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.

摘要翻译： 无边界通孔形成为与填充有HSQ的金属图案间隙的下部金属特征电连接。 在填充通孔之前，在惰性气氛中进行热处理，以排出在通孔的溶剂清洗期间吸收的水，从而通过空隙形成和通过完整性改善。

公开(公告)号：US08202810B2

公开(公告)日：2012-06-19

申请号：US11971331

申请日：2008-01-09

申请人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

发明人： Alexander H. Nickel ,  Allen L. Evans ,  Minh Quoc Tran ,  Lu You ,  Minh Van Ngo ,  Pei-Yuan Gao ,  William S. Brennan ,  Erik Wilson ,  Sung Jin Kim ,  Hieu Trung Pham

IPC分类号： H01L21/31

CPC分类号： H01L21/76877 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/76883 ,  Y10S438/902

摘要： A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

摘要翻译： 一种用于形成单个镶嵌和/或双镶嵌，接触和互连结构的方法，包括：执行前端处理，沉积包含铜屏障的铜，在至少90％的N 2中以小于10％的H 2退火铜，进行平面化 ，进行原位低H NH 3等离子体处理和低Si-H SiN蚀刻停止层沉积，并执行剩余的后端处理。

公开(公告)号：US20080108193A1

公开(公告)日：2008-05-08

申请号：US11593086

申请日：2006-11-06

申请人： Lu You ,  Alexander Nickel ,  Minh Q. Tran ,  Minh-Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Hirokazu Tokuno ,  Amir Hossein Jafarpour ,  Inkuk Kang ,  Robert Huertas

发明人： Lu You ,  Alexander Nickel ,  Minh Q. Tran ,  Minh-Van Ngo ,  Hieu Pham ,  Erik Wilson ,  Hirokazu Tokuno ,  Amir Hossein Jafarpour ,  Inkuk Kang ,  Robert Huertas

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/76883 ,  H01L27/11521

摘要： Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.

摘要翻译： 通过减少后端处理中的氢离子的产生和/或扩散（例如退火的Cu）来改善闪存器件（例如镜像位装置）中的数据保留。 实施方案包括在含有低H 2 N 2或无H 2 N的N 2 O 2气氛中以及在低于200℃的温度下退火嵌入的Cu， 例如，100℃至150℃

公开(公告)号：US20080096364A1

公开(公告)日：2008-04-24

申请号：US11582442

申请日：2006-10-18

申请人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

发明人： Erik Wilson ,  Minh-Van Ngo ,  Hieu Pham ,  Robert Huertas ,  Lu You ,  Hirokazu Tokuno ,  Alexander Nickel ,  Minh Tran

IPC分类号： H01L21/76

CPC分类号： H01L21/823468 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823437

摘要： Gap filling between features which are closely spaced is significantly improved by initially depositing a thin conformal layer followed by depositing a layer of gap filling dielectric material. Embodiments include depositing a thin conformal layer of silicon nitride or silicon oxide, as by atomic layer deposition or pulsed layer deposition, into the gap between adjacent gate electrode structures such that it flows into undercut regions of dielectric spacers on side surfaces of the gate electrode structures, and then depositing a layer of BPSG or P-HDP oxide on the thin conformal layer into the gap. Embodiments further include depositing the layers at a temperature less than 430° C., as by depositing a P-HDP oxide after depositing the conformal liner when the gate electrode structures include a layer of nickel silicide.

摘要翻译： 通过初始沉积薄的共形层，然后沉积一层间隙填充电介质材料，密切间隔的特征之间的间隙填充显着改善。 实施例包括通过原子层沉积或脉冲层沉积将氮化硅或氧化硅的薄保形层沉积到相邻栅电极结构之间的间隙中，使得其流到栅电极结构的侧表面上的电介质间隔物的底切区域 ，然后在薄的共形层上沉积一层BPSG或P-HDP氧化物到间隙中。 实施例还包括在低于430℃的温度下沉积层，如通过在栅极电极结构包括硅化镍层沉积保形衬垫之后沉积P-HDP氧化物。