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    Control systems having an address conversion device for controlling a cache memory and a cache tag memory
    1.
    发明授权
    Control systems having an address conversion device for controlling a cache memory and a cache tag memory 失效
    控制系统具有用于控制高速缓冲存储器的地址转换装置和高速缓存标签存储器

    公开(公告)号：US5584003A

    公开(公告)日：1996-12-10

    申请号：US575265

    申请日：1995-12-20

    申请人： Seiji Yamaguchi ,  Toru Kakiage ,  Tomohiro Kurozumi ,  Shiro Yoshioka ,  Koutarou Hirai

    发明人： Seiji Yamaguchi ,  Toru Kakiage ,  Tomohiro Kurozumi ,  Shiro Yoshioka ,  Koutarou Hirai

    IPC分类号： G06F12/10 ,  G06F12/00

    CPC分类号： G06F12/1054

    摘要： A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time. Further, this address conversion device controls a reading operation of the data stored in the cache memory by reading the physical address and the tag address at substantially the same time and by using a second control signal generated by the hit-signal generating circuit in synchronization with the word selecting signal. Moreover, the address conversion device controls the reading of data from the cache memory and the production of a cache hit signal, which is generated when the physical address matches the logical address. Accordingly, a high-performance system is achieved.

    摘要翻译： 用于控制高速缓存标签存储器的控制系统具有地址转换装置，其包括用于存储逻辑地址的关联存储器，用于存储物理地址的随机存取存储器和用于产生命中信号的命中信号产生电路，字选择信号 和至少一个控制信号。 命中信号指示在存储在关联存储器中的逻辑地址与输入逻辑地址之间发生命中。 地址转换装置通过使用由命中信号发生电路产生的控制信号与存储在存储器中的物理地址的读取操作中使用的字选择信号同步地控制存储在高速缓存标签存储器中的标签地址的读取操作 随机访问存储器，使得物理地址和标签地址在基本相同的时间被读取。 此外，该地址转换装置通过在同一时间读取物理地址和标签地址来控制存储在高速缓冲存储器中的数据的读取操作，并且通过使用由命中信号发生电路产生的第二控制信号与 字选择信号。 此外，地址转换装置控制从高速缓冲存储器的数据的读取和当物理地址与逻辑地址匹配时产生的高速缓存命中信号的产生。 因此，实现了高性能的系统。

    Microprocessor with dual-port cache memory for reducing penalty of consecutive memory address accesses
    2.
    发明授权
    Microprocessor with dual-port cache memory for reducing penalty of consecutive memory address accesses 失效
    具有双端口缓存存储器的微处理器，用于减少连续存储器地址访问的损失

    公开(公告)号：US5465344A

    公开(公告)日：1995-11-07

    申请号：US352445

    申请日：1994-12-09

    申请人： Koutarou Hirai ,  Seiji Yamaguchi

    发明人： Koutarou Hirai ,  Seiji Yamaguchi

    IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14

    CPC分类号： G06F12/0855 ,  G06F12/0853 ,  G06F12/0831

    摘要： A microprocessor has a CPU, an address converter which converts a logical address to a physical address, first and second latches which are controlled by a control signal and store the physical addresses, and a dual port cache memory device. The dual port cache memory device has decoders which operate according to second parts of outputs of the latches, dual port memory arrays which can be independently accessed by outputs of the decoders, a comparator which compares a physical address output from the dual port memory array and a first part of an output of the first latch to determine if they are the same, and a second comparator which compares a physical address output from the dual port memory array and a first part of an output of the second latch to determine if they are the same. The microprocessor is configured to effectively utilize the two ports of the dual port memory array of the dual port cache memory device, significantly improving the operating speed of the overall system by reducing the occurrence of penalties when consecutive instructions operating the cache memory are executed.

    摘要翻译： 微处理器具有CPU，将逻辑地址转换为物理地址的地址转换器，由控制信号控制并存储物理地址的第一和第二锁存器以及双端口高速缓存存储器件。 双端口高速缓冲存储器设备具有根据锁存器的输出的第二部分操作的解码器，可以由解码器的输出独立访问的双端口存储器阵列，将来自双端口存储器阵列的物理地址输出和 第一锁存器的输出的第一部分以确定它们是否相同;以及第二比较器，其比较来自双端口存储器阵列的物理地址输出和第二锁存器的输出的第一部分，以确定它们是否是 一样。 微处理器被配置为有效地利用双端口高速缓冲存储器设备的双端口存储器阵列的两个端口，通过在执行连续指令操作高速缓冲存储器时减少发生的惩罚，显着地提高整个系统的操作速度。

    Method and apparatus for manufacturing stator coil for electric rotating machine
    3.
    发明授权
    Method and apparatus for manufacturing stator coil for electric rotating machine 有权
    旋转电机定子线圈的制造方法和装置

    公开(公告)号：US08826713B2

    公开(公告)日：2014-09-09

    申请号：US13006678

    申请日：2011-01-14

    申请人： Akito Akimoto ,  Takuji Harada ,  Seiji Yamaguchi ,  Atsuo Ishizuka

    发明人： Akito Akimoto ,  Takuji Harada ,  Seiji Yamaguchi ,  Atsuo Ishizuka

    IPC分类号： B21B3/00 ,  B21F3/04 ,  H02K15/04 ,  H02K3/28

    CPC分类号： H02K3/28 ,  H02K15/0478 ,  Y10T29/49009

    摘要： A method of manufacturing a stator coil for an electric rotating machine includes the steps of: (1) forming substantially planar electric wires each of which includes in-slot portions to be received in slots of a stator core and turn portions to be located outside the slots to connect adjacent pairs of the in-slot portions; (2) rolling each of the planar electric wires through plastic deformation into a spiral or circular-arc shape; and (3) assembling the rolled electric wires together to form the stator coil. Further, in the rolling step, each of the planar electric wires is rolled by deforming each of the turn portions of the electric wire while restricting movement of at least one of the in-slot portions of the electric wire which is located closer to a rolling start end of the electric wire than the turn portion is.

    摘要翻译： 一种制造用于旋转电机的定子线圈的方法包括以下步骤：（1）形成基本上平面的电线，每个电线包括插槽部分以被接收在定子芯的槽中并且转动部分位于 槽以连接相邻的槽内部分; （2）通过塑性变形将每根平面电线卷成螺旋或圆弧形; 和（3）将轧制的电线组装在一起以形成定子线圈。 此外，在轧制步骤中，通过使电线的每个转弯部分变形，同时限制位于更接近轧制的电线的槽内部分的至少一个的运动，使每个平面电线卷绕 电线的开始端比转弯部分为止。

    Endoscope system
    4.
    发明授权
    Endoscope system 有权
    内窥镜系统

    公开(公告)号：US08465417B2

    公开(公告)日：2013-06-18

    申请号：US12273071

    申请日：2008-11-18

    申请人： Seiji Yamaguchi

    发明人： Seiji Yamaguchi

    IPC分类号： A61B1/018 ,  A61B1/0638 ,  A61B1/07 ,  A61B1/05 ,  H04N5/33

    CPC分类号： A61B1/3132 ,  A61B1/0005 ,  A61B1/042 ,  A61B1/045

    摘要： An endoscope system of the invention includes: a first endoscope capable of picking up an image of a subject; a first illuminating section capable of emitting first illuminating light; a second endoscope capable of picking up an image of the subject illuminated by the first light from a direction different from the first endoscope; a second illuminating section capable of emitting second illuminating light; a video signal processing section for generating a video signal based on a signal picked-up by the second endoscope; a display section for displaying an image of the subject obtained by the video signal processing section; an emphasis instructing section for instructing an emphasis on an image obtained based on the first light; and an emphasis control section for controlling to emphasize the subject image obtained based on the first light according to an operation of the emphasis instructing section.

    摘要翻译： 本发明的内窥镜系统包括：能够拾取被检体的图像的第一内窥镜; 能够发射第一照明光的第一照明部; 第二内窥镜，其能够从不同于所述第一内窥镜的方向拾取由所述第一光照射的被检体的图像; 能够发射第二照明光的第二照明部; 视频信号处理部分，用于基于由第二内窥镜拾取的信号产生视频信号; 用于显示由视频信号处理部分获得的被摄体的图像的显示部分; 强调指示部，用于指示强调基于第一光获得的图像; 以及强调控制部分，用于根据强调指示部分的操作来控制强调基于第一光获得的被摄体图像。

    Method for stabilizing calcium phosphates fine particles, method for manufacturing calcium phosphates fine particles by using the method, and use thereof
    5.
    发明授权
    Method for stabilizing calcium phosphates fine particles, method for manufacturing calcium phosphates fine particles by using the method, and use thereof 有权
    磷酸钙微粒的稳定化方法，使用该方法制造磷酸钙钙微粒的方法及其应用

    公开(公告)号：US08178066B2

    公开(公告)日：2012-05-15

    申请号：US11990432

    申请日：2006-08-15

    申请人： Takeshi Yao ,  Mitsuhiro Hibino ,  Seiji Yamaguchi ,  Hidetaka Okada

    发明人： Takeshi Yao ,  Mitsuhiro Hibino ,  Seiji Yamaguchi ,  Hidetaka Okada

    IPC分类号： C01B25/32 ,  C30B17/00 ,  C30B29/14

    CPC分类号： C01B25/327 ,  A61L27/12

    摘要： The present invention provides a method for stabilizing fine particles of calcium phosphates without lowering their solid phase forming activity.It is possible to stabilize the fine particles of calcium phosphates by stopping the growth of the fine particles formed in an aqueous solution supersaturated with respect to calcium phosphates. More specifically, the fine particles of calcium phosphates were stabilized by lowering the inorganic ion concentration of a fine-particle-forming solution containing fine particles of calcium phosphates by dialysis, ion exchange, dilution, or the like, or by separating the fine particles of calcium phosphates from the fine-particle-forming solution by filtration, centrifuging, or the like.

    摘要翻译： 本发明提供一种稳定磷酸钙细粒而不降低其固相形成活性的方法。 通过停止相对于磷酸钙过饱和的水溶液中形成的微粒的生长，可以稳定磷酸钙的微粒。 更具体地，通过透析，离子交换，稀释等降低含有磷酸钙微粒的微粒形成溶液的无机离子浓度，或者通过将 通过过滤，离心等形成细颗粒的溶液中的磷酸钙。