SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号:US20100289076A1

    公开(公告)日:2010-11-18

    申请号:US12808473

    申请日:2008-11-11

    IPC分类号: H01L29/78

    摘要: A technique is presented for further reducing on-resistance (or on-voltage) in a vertical semiconductor device provided with a carrier shielding layer.A semiconductor substrate 20 of a semiconductor device 10 comprises a channel section 10A and a non-channel section 10B. An emitter region 26 is formed in the channel section 10A, this emitter region 26 making contact with a side surface of a trench gate 30 and being electrically connected to an emitter electrode 28. The emitter region 26 is not formed in a body region 25 of the non-channel section 10B. In a plan view, an occupied area ratio of the area which a carrier shielding layer 52 located in the non-channel section 10B occupies within the non-channel section 10B is larger than an occupied area ratio of the area which the carrier shielding layer 52 located in the channel section 10A occupies within the channel section 10A.

    摘要翻译: 提出了一种技术,用于在具有载体屏蔽层的垂直半导体器件中进一步降低导通电阻(或导通电压)。 半导体器件10的半导体衬底20包括沟道部分10A和非沟道部分10B。 发射极区域26形成在沟道部分10A中,该发射极区域26与沟槽栅极30的侧表面接触并且电连接到发射极电极28.发射极区域26不形成在 非通道部分10B。 在平面图中,位于非通道部10B中的载流子屏蔽层52所占据的区域的占用面积比大于非沟道部分10B中的载流子屏蔽层52所占的面积比 位于通道部分10A中的通道部分10A占据通道部分10A。