公开(公告)号：US5508549A

公开(公告)日：1996-04-16

申请号：US735948

申请日：1991-07-25

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

公开(公告)号：US5049967A

公开(公告)日：1991-09-17

申请号：US631907

申请日：1990-12-21

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from a surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

公开(公告)号：US5672897A

公开(公告)日：1997-09-30

申请号：US462902

申请日：1995-06-05

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78 ,  H01L29/76 ,  H01L29/167

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

摘要翻译： 提供了一种改进的布置，用于在具有CMOS元件的衬底上形成双极晶体管。 所有晶体管（即，双极型，P-MOS和N-MOS）形成在从表面朝向衬底的杂质浓度逐渐降低的区域中。 此外，在形成晶体管的杂质浓度降低的各个区域的下方设置掩埋层。 这些掩埋层的杂质浓度明显高于杂质浓度下降的部分。 使用这种布置，防止了穿通，并且为双极晶体管和CMOS元件都提供了优异的电操作特性。

公开(公告)号：US4980744A

公开(公告)日：1990-12-25

申请号：US159956

申请日：1988-02-24

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

公开(公告)号：US4921811A

公开(公告)日：1990-05-01

申请号：US176284

申请日：1988-03-31

申请人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

发明人： Atsuo Watanabe ,  Takahide Ikeda ,  Kiyoshi Tsukuda ,  Mitsuru Hirao ,  Touji Mukai ,  Tatsuya Kamei

IPC分类号： H01L27/08 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/118 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L27/11896 ,  H01L21/8249 ,  H01L27/0623

摘要： An improved arrangement is provided for forming a bipolar transistor on a substrate with CMOS elements. All of the transistors (i.e., the bipolar, P-MOS and N-MOS) are formed in regions having gradually decreasing impurity concentrations from the surface toward the substrate. In addition, a buried layer is provided under each of the regions of decreasing impurity concentration in which the transistors are formed. These buried layers have a significantly higher impurity concentration than the portion of the region of decreasing impurity concentration which they are respectively adjacent to. Using this arrangement, punch-through is prevented and excellent electrical operating characteristics are provided for both the bipolar transistors and the CMOS elements.

摘要翻译： 提供了一种改进的布置，用于在具有CMOS元件的衬底上形成双极晶体管。 所有晶体管（即，双极型，P-MOS和N-MOS）形成在从表面朝向衬底的杂质浓度逐渐降低的区域中。 此外，在形成晶体管的杂质浓度降低的各个区域的下方设置掩埋层。 这些掩埋层的杂质浓度明显高于杂质浓度下降的部分。 使用这种布置，防止了穿通，并且为双极晶体管和CMOS元件都提供了优异的电操作特性。

公开(公告)号：US4799098A

公开(公告)日：1989-01-17

申请号：US37123

申请日：1987-04-10

申请人： Takahide Ikeda ,  Atsuo Watanabe ,  Touji Mukai ,  Masanori Odaka ,  Katsumi Ogiue

发明人： Takahide Ikeda ,  Atsuo Watanabe ,  Touji Mukai ,  Masanori Odaka ,  Katsumi Ogiue

IPC分类号： H01L29/78 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/73 ,  H01L27/02

CPC分类号： H01L21/74 ,  H01L21/8249 ,  H01L27/0623

摘要： In a semiconductor device of the type in which a bipolar element and MOS field-effect transistors are formed on one surface of a semiconductor substrate, this invention discloses a semiconductor device characterized in that first buried layers of a first conductivity type are formed within regions of the semiconductor substrate in which the bipolar element are formed, a second buried layer of the first conductivity and at least one MOS field-effect transistor type is formed within the semiconductor substrate facing at least the emitter of the bipolar element, and the depth from one surface of the semiconductor substrate to the second buried layer of the first conductivity type is less than the depth from that surface to the first buried layer of the first conductivity type.This invention can prevent any increase in the capacity of the MOS field-effect transistor, and can also improve the operating speed of the bipolar element.

摘要翻译： 在半导体衬底的一个表面上形成双极性元件和MOS场效应晶体管的半导体器件中，本发明公开了一种半导体器件，其特征在于，在第 其中形成双极元件的半导体衬底，第一导电性的第二掩埋层和至少一个MOS场效应晶体管类型形成在面向至少双极元件的发射极的半导体衬底内，并且从一个 第一导电类型的第二掩埋层的半导体衬底的表面小于从该表面到第一导电类型的第一掩埋层的深度。 本发明可以防止MOS场效应晶体管的容量的任何增加，并且还可以提高双极元件的工作速度。