公开(公告)号：US06767768B2

公开(公告)日：2004-07-27

申请号：US10328367

申请日：2002-12-23

申请人： Tsong-Minn Hsieh

发明人： Tsong-Minn Hsieh

IPC分类号： H01L2182

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then, another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer. Next, a second dielectric layer is formed on the first electrode and an intentionally misaligned process is performed to second dielectric layer to form an antifuse via open, such that the breakdown will be occurred on the corner of the first via, wherein the antifuse via open intentionally misaligned to the conductive plug. Then, a third dielectric layer and a second electrode of the capacitor are subsequently formed on the portion of the second dielectric layer and on sidewall of the antifuse via open. Finally, a second conductive wire is formed on the second electrode.

公开(公告)号：US06657277B1

公开(公告)日：2003-12-02

申请号：US10199358

申请日：2002-07-19

申请人： Tsong-Minn Hsieh

发明人： Tsong-Minn Hsieh

IPC分类号： H01L2904

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer. Next, a second dielectric layer is formed on the first electrode and an intentionally misaligned process is performed to second dielectric layer to form an antifuse via open, such that the breakdown will be occurred on the corner of the first via, wherein the antifuse via open intentionally misaligned to the conductive plug. Then, a third dielectric layer and a second electrode of the capacitor are subsequently formed on the portion of the second dielectric layer and on sidewall of the antifuse via open. Finally, a second conductive wire is formed on the second electrode.

摘要翻译： 本发明提供一种形成反熔丝通孔结构的方法。 反熔丝通孔结构包括其中具有第一导电线的基板。 然后，在基板上形成第一电介质层，在第一电介质层上形成光致抗蚀剂层。 接下来，执行蚀刻工艺以蚀刻第一介电层以在第一介电层中形成通孔。 然后，沉积第一导电层以填充通孔，并执行抛光工艺以形成导电塞，其中导电塞在第一导线上。 接下来，沉积在部分第一介电层上和导电塞表面上的缓冲层。 然后对缓冲层进行另一抛光处理以暴露导电塞的部分。 此后，电容器的第一电极沉积在缓冲层上。 接下来，在第一电极上形成第二电介质层，并且对第二电介质层进行有意的不对准处理，以形成反熔丝通孔，使得击穿将发生在第一通孔的拐角处，其中反熔丝通孔 故意不对准导电插头。 然后，第二电介质层的部分和反熔丝的侧壁经由开口随后形成电容器的第三电介质层和第二电极。 最后，在第二电极上形成第二导线。

公开(公告)号：US06414350B1

公开(公告)日：2002-07-02

申请号：US09460081

申请日：1999-12-14

申请人： Tsong-Minn Hsieh ,  Kuo-Tung Sung

发明人： Tsong-Minn Hsieh ,  Kuo-Tung Sung

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  Y10S257/90

摘要： A split gate EPROM cell and a method that includes a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. Controlling the thickness of the spacer allows avoiding a reduction of the distance between the floating gate and the control gate as well as leakage of the charge from the floating gate.

摘要翻译： 一个分裂栅极EPROM单元和一种方法，其包括具有围绕浮动栅极设置的差分组成的侧壁间隔物的栅极结构，其有利于在制造期间控制间隔物厚度。 控制间隔物的厚度允许避免浮动栅极和控制栅极之间的距离的减小以及电荷从浮动栅极泄漏。

公开(公告)号：US06245614B1

公开(公告)日：2001-06-12

申请号：US09597745

申请日：2000-06-19

申请人： Tsong-Minn Hsieh

发明人： Tsong-Minn Hsieh

IPC分类号： H01L218247

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/78

摘要： A method of manufacturing a self-aligned split-gate flash memory cell with high coupling ratio is disclosed. A polysilicon spacer is first formed on each of the inner walls between the two select gates on which a dielectric layer is formed. A drain and a source are next formed adjacent to each of the outer walls of the two select gates and between the two polysilicon spacers, respectively. A silicon oxide layer is deposited. A predetermined thickness of the silicon oxide layer is then removed and the dielectric layer is removed down to a predetermined thickness by using a dry etching process. Finally, a control gate is formed above the polysilicon spacers.

摘要翻译： 公开了一种制造具有高耦合比的自对准分离式快门存储器单元的方法。 首先在其上形成介电层的两个选择栅极之间的每个内壁上形成多晶硅间隔物。 接下来，分别在两个选择栅极的每个外壁和两个多晶硅间隔件之间形成漏极和源极。 沉积氧化硅层。 然后去除氧化硅层的预定厚度，并且通过使用干蚀刻工艺将电介质层去除到预定厚度。 最后，在多晶硅间隔物上形成一个控制栅极。

公开(公告)号：US06894364B2

公开(公告)日：2005-05-17

申请号：US10248833

申请日：2003-02-24

申请人： Ming-Yin Hao ,  Tri-Rung Yew ,  Coming Chen ,  Tsong-Minn Hsieh ,  Nai-Chen Peng ,  Jih-Cheng Yeh

发明人： Ming-Yin Hao ,  Tri-Rung Yew ,  Coming Chen ,  Tsong-Minn Hsieh ,  Nai-Chen Peng ,  Jih-Cheng Yeh

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L28/60 ,  H01L21/76807 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

摘要翻译： 描述了在互连系统中具有电容器的集成器件的制造方法。 至少第一露出金属线和第二金属线设置在绝缘层中。 堆叠层并图案化以在第二金属线上形成膜堆叠结构。 在膜堆叠结构，第一金属线和绝缘层之上形成金属间介电层。 至少第一双镶嵌互连和第二双镶嵌互连分别形成在第一金属线和薄膜堆叠结构的上方并与之接触。

公开(公告)号：US06326263B1

公开(公告)日：2001-12-04

申请号：US09636557

申请日：2000-08-11

申请人： Tsong-Minn Hsieh

发明人： Tsong-Minn Hsieh

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324

摘要： A semiconductor wafer is provided having a substrate, and a tunneling oxide layer is formed thereon. A sacrificial layer defining an active region is formed over the tunneling oxide layer, and a defined first polysilicon layer is formed on the tunneling oxide layer within the active region and covered by the sacrificial layer. The process sequence includes: performing an etching process using the sacrificial layer as a mask to form a STI pattern, forming a dielectric layer that fills the STI pattern, performing a planarization process to remove the dielectric layer over the sacrificial layer, performing a first etch back process to remove a pre-selected thickness of the dielectric layer over the STI pattern, forming a second polysilicon layer, performing a second etch back process to form a spacer connecting with the first polysilicon layer, removing the sacrificial layer, forming an insulating layer on the surface of the spacer and the first polysilicon layer, forming a control gate on the insulating layer, and performing an ion implantation process to form a source and a drain on the substrate within the active region.

摘要翻译： 提供具有基板的半导体晶片，并且在其上形成隧道氧化物层。 在隧穿氧化物层上形成限定有源区的牺牲层，并且在有源区内的隧道氧化物层上形成限定的第一多晶硅层，并被牺牲层覆盖。 处理顺序包括：使用牺牲层作为掩模进行蚀刻处理以形成STI图案，形成填充STI图案的介电层，执行平坦化处理以去除牺牲层上的电介质层，执行第一蚀刻 去除STI图案上的电介质层的预选厚度，形成第二多晶硅层，执行第二回蚀工艺以形成与第一多晶硅层连接的间隔物，去除牺牲层，形成绝缘层 在所述间隔物的表面和所述第一多晶硅层上，在所述绝缘层上形成控制栅极，并且进行离子注入工艺以在所述有源区域内的所述衬底上形成源极和漏极。

公开(公告)号：US06617233B2

公开(公告)日：2003-09-09

申请号：US09998263

申请日：2001-11-30

申请人： Tsong-Minn Hsieh ,  Ruey Jiunn Guo

发明人： Tsong-Minn Hsieh ,  Ruey Jiunn Guo

IPC分类号： H01L2144

CPC分类号： H01L23/5252 ,  H01L21/76877 ,  H01L2924/0002 ,  Y10S438/978 ,  H01L2924/00

摘要： A process of forming an anti-fuse. First, an inter-metal dielectric layer, in which a funnel-shaped via is formed, is formed on a substrate. Next, a first conductive layer is formed over the substrate and filled into the funnel-shaped via. Subsequently, by, for example, a chemical mechanical polishing process, the first conductive layer outside the funnel-shaped via is removed to form a conductive plug. Afterward, an oxide chemical mechanical polishing process is performed to smooth the surface of the conductive plug. Next, a dielectric layer is formed on the top side of the conductive plug, and then a top plate is formed on the dielectric layer. Subsequently, an insulating layer is formed over the substrate, wherein the insulating layer is provided with a via and the via exposes the top plate. Finally, a second conductive layer is formed over the substrate and filled into the via.

摘要翻译： 形成抗熔丝的工艺。 首先，在基板上形成有形成漏斗状的通路的金属间介电层。 接下来，在衬底上形成第一导电层并填充到漏斗形通孔中。 随后，通过例如化学机械抛光工艺，去除漏斗形通孔外部的第一导电层以形成导电塞。 之后，进行氧化物化学机械抛光工艺以平滑导电塞的表面。 接下来，在导电插塞的顶侧形成电介质层，然后在电介质层上形成顶板。 随后，在衬底上形成绝缘层，其中绝缘层设置有通孔，并且通孔暴露顶板。 最后，在衬底上形成第二导电层并填充到通孔中。

公开(公告)号：US06498030B2

公开(公告)日：2002-12-24

申请号：US09925337

申请日：2001-08-09

申请人： Tsong-Minn Hsieh

发明人： Tsong-Minn Hsieh

IPC分类号： H01L29788

CPC分类号： H01L27/11556 ,  H01L27/115

摘要： The structure of a flash memory is described. Device isolation structures are located on the substrate. Sources are provided on the top layer of the substrate between two device isolation structures. Tunneling oxide layers are provided at both ends of the device isolation structures and on the substrate where the sources are present. Drains are provided in the top layer of the substrate where the tunneling oxide layer is absent in between the device isolation structures. Polysilicon blocks are extended across the ends of two device isolating structures, above the tunnel oxide layer. A silicon oxide cap layer is located on the polysilicon block. The silicon oxide layers are formed on the sidewalls of the polysilicon blocks. The polysilicon layer is on the sidewall of the polysilicon blocks and the polysilicon blocks are separated by the silicon oxide layer. The silicon oxide layer covers the surface of the polysilicon layers. Another polysilicon layer, which is located on the tunnel silicon oxide layer above the sources also, covers a part of the silicon oxide cap layer.

公开(公告)号：US06465838B1

公开(公告)日：2002-10-15

申请号：US09630868

申请日：2000-08-02

申请人： Tsong-Minn Hsieh

发明人： Tsong-Minn Hsieh

IPC分类号： H01L29788

CPC分类号： H01L27/11556 ,  H01L27/115

摘要： The structure of a flash memory is described. Device isolation structures are located on the substrate. Sources are provided on the top layer of the substrate between two device isolation structures. Tunneling oxide layers are provided at both ends of the device isolation structures and on the substrate where the sources are present. Drains are provided in the top layer of the substrate where the tunneling oxide layer is absent in between the device isolation structures. Polysilicon blocks are extended across the ends of two device isolating structures, above the tunnel oxide layer. A silicon oxide cap layer is located on the polysilicon block. The silicon oxide layers are formed on the sidewalls of the polysilicon blocks. The polysilicon layer is on the sidewall of the polysilicon blocks and the polysilicon blocks are separated by the silicon oxide layer. The silicon oxide layer covers the surface of the polysilicon layers. Another polysilicon layer, which is located on the tunnel silicon oxide layer above the sources also, covers a part of the silicon oxide cap layer.

公开(公告)号：US06436764B1

公开(公告)日：2002-08-20

申请号：US09590721

申请日：2000-06-08

申请人： Tsong-Minn Hsieh

发明人： Tsong-Minn Hsieh

IPC分类号： H01L218242

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method for forming self-aligned split gates in a flesh memory is disclosed. The method includes two-step lithographic definition of a split gate and nitride spacer formation of the gate. The two-step lithography procedure is designed to assist the nitride spacer formation. The nitride spacer formation is used to facilitate gate etching in a self-aligned manner so that the channel length of the split gate is under proper control and the effect of gate misalignment can be totally avoided. The product quality of the flesh memory therefore gets improved.

摘要翻译： 公开了一种用于在肉体存储器中形成自对准分裂门的方法。 该方法包括分离栅极和栅极的氮化物间隔物形成的两步光刻定义。 两步光刻工艺旨在帮助氮化物间隔物的形成。 氮化物间隔物形成用于以自对准的方式促进栅极蚀刻，使得分裂栅极的沟道长度得到适当的控制，并且可以完全避免栅极失准的影响。 因此，肉体记忆的产品质量得到改善。