公开(公告)号：US06414350B1

公开(公告)日：2002-07-02

申请号：US09460081

申请日：1999-12-14

申请人： Tsong-Minn Hsieh ,  Kuo-Tung Sung

发明人： Tsong-Minn Hsieh ,  Kuo-Tung Sung

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  Y10S257/90

摘要： A split gate EPROM cell and a method that includes a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. Controlling the thickness of the spacer allows avoiding a reduction of the distance between the floating gate and the control gate as well as leakage of the charge from the floating gate.

摘要翻译： 一个分裂栅极EPROM单元和一种方法，其包括具有围绕浮动栅极设置的差分组成的侧壁间隔物的栅极结构，其有利于在制造期间控制间隔物厚度。 控制间隔物的厚度允许避免浮动栅极和控制栅极之间的距离的减小以及电荷从浮动栅极泄漏。

公开(公告)号：US6054350A

公开(公告)日：2000-04-25

申请号：US54358

申请日：1998-04-02

申请人： Tsong-Minn Hsieh ,  Kuo-Tung Sung

发明人： Tsong-Minn Hsieh ,  Kuo-Tung Sung

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L29/66825 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  Y10S257/90

摘要： A split gate EPROM cell and a method that includes a gate structure having a sidewall spacer of differential composition disposed about a floating gate which facilitates control of the spacer thickness during fabrication. Controlling the thickness of the spacer allows avoiding a reduction of the distance between the floating gate and the control gate as well as leakage of the charge from the floating gate.

摘要翻译： 一个分裂栅极EPROM单元和一种方法，其包括具有围绕浮动栅极设置的差分组成的侧壁间隔物的栅极结构，其有利于在制造期间控制间隔物厚度。 控制间隔物的厚度允许避免浮动栅极和控制栅极之间的距离的减小以及电荷从浮动栅极泄漏。

公开(公告)号：US06331721B1

公开(公告)日：2001-12-18

申请号：US09264210

申请日：1999-03-05

申请人： Kuo-Tung Sung ,  Wen-Ting Chu ,  Huoy-Jong Wu

发明人： Kuo-Tung Sung ,  Wen-Ting Chu ,  Huoy-Jong Wu

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42328

摘要： An E2PROM or a flash memory cell having a sharp tip or thin wedge at one of its gates, e.g., the floating gate, for the erasure of electrical charges stored in the floating gate. A recess is formed between a first polysilicon gate and the substrate by removing portions of an insulating layer interposed between the first gate and the substrate. Another insulating layer, e.g., thermal oxide, is formed on the exposed portions of the first gate and the substrate, and partially fills the recess. A second polysilicon layer is formed on the thermal oxide and patterned to form a floating gate. The partially filled recess causes a sharp polysilicon tip or thin wedge to be formed as part of the floating gate. This sharp tip or thin wedge can generate a high electrical field that facilitates the removal of the stored electrical charges from the floating gate.

摘要翻译： E2PROM或闪存单元在其门之一（例如浮置栅极）处具有尖锐尖端或薄楔形，用于擦除存储在浮动栅极中的电荷。 通过去除介于第一栅极和衬底之间的绝缘层的部分，在第一多晶硅栅极和衬底之间形成凹部。 在第一栅极和衬底的暴露部分上形成另一绝缘层，例如热氧化物，并且部分地填充凹部。 第二多晶硅层形成在热氧化物上并被图案化以形成浮栅。 部分填充的凹槽使得形成尖锐的多晶硅尖端或薄楔形物作为浮动栅极的一部分。 这个尖锐的尖端或薄的楔子可以产生高电场，便于从浮动栅极去除存储的电荷。

公开(公告)号：US06194272B1

公开(公告)日：2001-02-27

申请号：US09093841

申请日：1998-05-19

申请人： Kuo-Tung Sung

发明人： Kuo-Tung Sung

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42332 ,  Y10S438/951

摘要： A dual-gate cell structure with self-aligned gates. A polysilicon spacer forms a second gate (213) separated from a first gate (201), which is also polysilicon, by a dielectric layer (207). A drain region (219) and a source region (221) are formed next to the gates. In one embodiment, the second gate (213) acts as a floating gate in a flash cell. The floating gate may be programmed and erased by the application of appropriate voltage levels to the first gate (201), source (221), and/or drain (219). The self-aligned nature of the second gate (213) to the first gate (201) allows a very small dual-gate cell to be formed.

摘要翻译： 具有自对准门的双门单元结构。 多晶硅间隔物通过介电层（207）形成与也是多晶硅的第一栅极（201）分离的第二栅极（213）。 漏极区域（219）和源极区域（221）形成在栅极附近。 在一个实施例中，第二栅极（213）用作闪存单元中的浮动栅极。 可以通过向第一栅极（201），源极（221）和/或漏极（219）施加适当的电压电平来对浮动栅极进行编程和擦除。 第二栅极（213）到第一栅极（201）的自对准性质允许形成非常小的双栅极单元。

公开(公告)号：US6136647A

公开(公告)日：2000-10-24

申请号：US856057

申请日：1997-05-14

申请人： Kuo-Tung Sung

发明人： Kuo-Tung Sung

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/28273

摘要： A method of fabricating an interpoly dielectric layer and a gate oxide layer of a programmable memory device. This method allows a gate oxide layer and a top oxide layer of the interpoly dielectric layer to be formed simultaneously by two consecutive processes, and essentially comprises the following steps: (1) forming a bottom oxide and a nitride layer of the interpoly dielectric layer on a floating gate of the memory device; (2) defining a gate oxide growing region on the interpoly dielectric layer with a photoresist mask; (3) etching the nitride and bottom oxide layer over the area defined as the gate oxide growth region; (4) forming a first oxide layer on the gate oxide growth region and the nitride of the interpoly dielectric layer above the floating gate; and (5) forming a second oxide layer on the first oxide layer to serve simultaneously as part of the top oxide layer of the interpoly dielectric layer and as part of the gate oxide layer.

摘要翻译： 一种制造可编程存储器件的间隔电介质层和栅氧化层的方法。 该方法允许通过两个连续工艺同时形成间隔电介质层的栅极氧化物层和顶部氧化物层，并且基本上包括以下步骤：（1）将层间电介质层的底部氧化物和氮化物层形成在 存储器件的浮动栅极; （2）利用光致抗蚀剂掩模在间隔电介质层上限定栅极氧化层生长区; （3）在限定为栅极氧化物生长区域的区域上蚀刻氮化物和底部氧化物层; （4）在所述栅极氧化物生长区上形成第一氧化物层，在所述浮栅之上形成所述多晶硅互连电介质层的氮化物; 和（5）在所述第一氧化物层上形成第二氧化物层，以同时用作所述互聚电介质层的顶部氧化物层的一部分并且作为所述栅极氧化物层的一部分。

公开(公告)号：US08217469B2

公开(公告)日：2012-07-10

申请号：US12701649

申请日：2010-02-08

申请人： Yung-Chin Hou ,  Yuh-Jier Mii ,  Kuo-Tung Sung ,  Li-Chun Tien

发明人： Yung-Chin Hou ,  Yuh-Jier Mii ,  Kuo-Tung Sung ,  Li-Chun Tien

IPC分类号： H01L27/088

CPC分类号： H01L27/0207 ,  H01L21/823871 ,  H01L29/4238 ,  Y10S257/90

摘要： The present disclosure provides a device in an integrated circuit. The device includes an active region in a semiconductor substrate; an isolation region adjacent the active region; a gate disposed on the active region and extending to the isolation region in a first direction; and a gate contact disposed within the isolation region, having a portion directly overlying and contacting the gate, and having a geometry horizontally extending to a first dimension in the first direction and a second dimension in a second direction approximately perpendicular to the first direction. The first dimension is greater than the second dimension.

摘要翻译： 本公开提供了一种集成电路中的器件。 该器件包括半导体衬底中的有源区; 邻近有源区的隔离区; 设置在所述有源区上并在第一方向延伸到所述隔离区的栅极; 以及设置在所述隔离区域内的栅极接触件，其具有直接覆盖并接触所述栅极的部分，并且具有水平延伸到所述第一方向上的第一尺寸的几何形状，以及大致垂直于所述第一方向的第二方向的第二尺寸。 第一个维度大于第二个维度。

公开(公告)号：US6121116A

公开(公告)日：2000-09-19

申请号：US041834

申请日：1998-03-12

申请人： Kuo-Tung Sung

发明人： Kuo-Tung Sung

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11526 ,  H01L21/76202 ,  H01L27/11529 ,  H01L27/11531 ,  H01L29/42324

摘要： The present invention provides novel isolation regions (501, 215) in a flash memory integrated circuit device. The isolation regions (501, 215) are formed on a silicon substrate (201), which has a core memory region (e.g., flash memory cell region) and a high voltage region (e.g., high voltage MOS device region). A silicon dioxide layer (e.g., silicon dioxide, silicon oxynitride) (203) is defined overlying the substrate including both of the regions. A nitride mask layer (205) is formed overlying the silicon dioxide layer in the core memory region and the high voltage region. This nitride mask layer exposes (207) a first isolation region coupled to the high voltage region. The first isolation region includes a first isolation structure having a first thickness of silicon dioxide. A step of oxidizing an exposed second isolation region to form the second isolation structure (215) and simultaneously oxidizing the first isolation structure to a second thickness is included.

摘要翻译： 本发明在闪速存储器集成电路器件中提供了新的隔离区（501,215）。 隔离区（501,215）形成在具有核存储区（例如闪存单元区）和高电压区（例如，高电压MOS器件区））的硅衬底（201）上。 二氧化硅层（例如，二氧化硅，氮氧化硅）（203）被限定在包括两个区域的基板上。 在芯存储区域和高电压区域中形成覆盖二氧化硅层的氮化物掩模层（205）。 该氮化物掩模层暴露（207）耦合到高电压区域的第一隔离区域。 第一隔离区域包括具有第一厚度二氧化硅的第一隔离结构。 包括氧化暴露的第二隔离区以形成第二隔离结构（215）并同时将第一隔离结构氧化成第二厚度的步骤。

公开(公告)号：US5917214A

公开(公告)日：1999-06-29

申请号：US31264

申请日：1998-02-26

申请人： Kuo-Tung Sung

发明人： Kuo-Tung Sung

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A split gate flash memory unit comprises a silicon substrate; a first insulating layer formed on said silicon substrate; a first conductive layer formed on a part area of said first insulating layer; a second insulating layer formed on left and right sidewalls of said first conductive layer and on another part area of said first insulating layer; a third insulating layer formed on said first conductive layer. The third insulating layer is also formed on said second insulating layer located at said left and right side walls of the first conductive layer in order to reduce an asperity effect on left and right edges of said first conductive layer. A second conductive layer is formed on said second and third insulating layers for being isolated from said first conductive layer by a blocking function of said second and third insulating layer.

摘要翻译： 分离栅极闪存单元包括硅衬底; 形成在所述硅衬底上的第一绝缘层; 形成在所述第一绝缘层的一部分区域上的第一导电层; 形成在所述第一导电层的左侧壁和所述第二绝缘层的另一部分区域上的第二绝缘层; 形成在所述第一导电层上的第三绝缘层。 第三绝缘层也形成在位于第一导电层的左侧壁和右侧壁的所述第二绝缘层上，以便减小对所述第一导电层的左边缘和右边缘的粗糙度影响。 在所述第二和第三绝缘层上形成第二导电层，以通过所述第二和第三绝缘层的阻挡功能与所述第一导电层隔离。

公开(公告)号：US5789296A

公开(公告)日：1998-08-04

申请号：US764612

申请日：1996-12-05

申请人： Kuo-Tung Sung ,  Chih-Hsun Chu

发明人： Kuo-Tung Sung ,  Chih-Hsun Chu

IPC分类号： H01L21/336 ,  H01L21/8247

CPC分类号： H01L29/66825

摘要： A method for forming a structure of a split gate flash memory is provided. The method includes steps of: a) preparing a substrate having an oxide layer; b) forming a first conducting layer over the oxide layer; c) etching a portion of the first conducting layer to form a word line structure for the flash memory; d) forming a spacer layer over the word line structure to be a side-wall portion of a word-line protecting layer; e) oxidizing the word-line protecting layer to form a dielectric layer; and f) forming a floating gate layer over the dielectric layer.

摘要翻译： 提供了一种用于形成分离栅闪存的结构的方法。 该方法包括以下步骤：a）制备具有氧化物层的衬底; b）在所述氧化物层上形成第一导电层; c）蚀刻第一导电层的一部分以形成闪存的字线结构; d）在字线结构上形成间隔层，以形成字线保护层的侧壁部分; e）氧化字线保护层以形成电介质层; 以及f）在所述电介质层上形成浮栅层。

公开(公告)号：US5783473A

公开(公告)日：1998-07-21

申请号：US777276

申请日：1997-01-06

申请人： Kuo-Tung Sung

发明人： Kuo-Tung Sung

IPC分类号： H01L21/336 ,  H01L29/423 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L29/42324

摘要： A split gate flash memory manufacturing process comprises the steps of: (a) providing a silicon substrate having a first insulating layer, and forming a first conductive layer on said first insulating layer, and forming a third insulating layer on said first conductive layer; (b) removing part of said third insulating layer and part of said first conductive layer to expose left and right sidewalls of said first conductive layer and part area of said first insulating layer; (c) performing an oxidation process to form a second insulating layer on left and right sidewalls of said first conductive layer and on said part area of said first insulating layer, wherein by a blocking function of the third insulating layer on said second insulating layer an asperity effect on left and right edges of said first conductive layer is reduced; and (d) forming a second conductive layer on said second and third insulating layers to form said split gate flash memory unit.

摘要翻译： 分离栅闪存制造方法包括以下步骤：（a）提供具有第一绝缘层的硅衬底，并在所述第一绝缘层上形成第一导电层，以及在所述第一导电层上形成第三绝缘层; （b）去除所述第三绝缘层的一部分和所述第一导电层的一部分，以暴露所述第一导电层的左侧壁和右侧壁以及所述第一绝缘层的部分区域; （c）进行氧化处理以在所述第一导电层的左侧壁和所述第一绝缘层的所述部分区域上形成第二绝缘层，其中通过所述第二绝缘层上的第三绝缘层的阻挡功能， 对所述第一导电层的左右边缘的粗糙度影响减小; 和（d）在所述第二和第三绝缘层上形成第二导电层以形成所述分离栅极闪存单元。