公开(公告)号：US06894364B2

公开(公告)日：2005-05-17

申请号：US10248833

申请日：2003-02-24

申请人： Ming-Yin Hao ,  Tri-Rung Yew ,  Coming Chen ,  Tsong-Minn Hsieh ,  Nai-Chen Peng ,  Jih-Cheng Yeh

发明人： Ming-Yin Hao ,  Tri-Rung Yew ,  Coming Chen ,  Tsong-Minn Hsieh ,  Nai-Chen Peng ,  Jih-Cheng Yeh

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L29/00 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L28/60 ,  H01L21/76807 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fabrication method for an integrated device having a capacitor in an interconnect system is described. At least a first exposed metal line and a second metal line are provided in an insulating layer. A stack layer is deposited and patterned to form a film stack structure over the second metal line. An inter-metal dielectric layer is formed over the film stack structure, the first metal line and the insulating layer. At least a first dual damascene interconnect and a second dual damascene interconnect are formed over and in contact with the first metal line and the film stack structure, respectively.

摘要翻译： 描述了在互连系统中具有电容器的集成器件的制造方法。 至少第一露出金属线和第二金属线设置在绝缘层中。 堆叠层并图案化以在第二金属线上形成膜堆叠结构。 在膜堆叠结构，第一金属线和绝缘层之上形成金属间介电层。 至少第一双镶嵌互连和第二双镶嵌互连分别形成在第一金属线和薄膜堆叠结构的上方并与之接触。

公开(公告)号：US07511329B2

公开(公告)日：2009-03-31

申请号：US10906535

申请日：2005-02-24

申请人： Chien-Hung Chen ,  Nai-Chen Peng ,  Kuang-Pi Lee ,  Tzu-Ping Chen

发明人： Chien-Hung Chen ,  Nai-Chen Peng ,  Kuang-Pi Lee ,  Tzu-Ping Chen

IPC分类号： H01L23/62

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

摘要： A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements, an insulating layer positioned on surfaces and sidewalls of the control gates, and a bit-line positioned on the insulating layer to cross the control gates.

摘要翻译： 非易失性存储器包括基板，位于基板上的多个数据存储元件，位于数据存储元件上方的多个控制栅极，位于控制栅极的表面和侧壁上的绝缘层，以及位线 位于绝缘层上以跨越控制门。

公开(公告)号：US20060109713A1

公开(公告)日：2006-05-25

申请号：US10996204

申请日：2004-11-22

申请人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

发明人： Ching-Hung Cheng ,  Nai-Chen Peng ,  Chung-Chin Shih ,  Tzyh-Cheang Lee

IPC分类号： G11C16/04

CPC分类号： H01L27/11568 ,  G11C16/0433 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/24 ,  H01L27/115

摘要： A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

摘要翻译： 提供了包括多个字线，多个位线，至少四个控制线和多个存储器单元的存储器件。 位线沿着字线的垂直方向设置。 每个存储单元设置在一条字线和一条位线之间的交叉点，并且具有公共字线的每四个顺序存储单元分别连接到四条控制线。 此外，在每个存储单元中，其控制线设置在其位线和字线之间，并且与其位线平行，其中存储单元中的每一个被设置为位。

公开(公告)号：US07193265B2

公开(公告)日：2007-03-20

申请号：US10907006

申请日：2005-03-16

申请人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

发明人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

摘要： The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

摘要翻译： 单多晶硅EEPROM包括串联连接到第二PMOS晶体管的第一PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括浮置栅极，第一P + +掺杂漏极区域和第一P + +掺杂源极区域。 第二PMOS晶体管包括栅极和第二P + +掺杂源极区域。 第一PMOS晶体管的第一P + SUP掺杂漏区用作第二PMOS晶体管的漏极。 二极管位于包括P阱和N + +掺杂区的P型衬底中。 浮栅与N阱重叠并延伸到N + +掺杂区。 浮置栅极下面的P阱和N + + / / P>掺杂区域结的重叠区域用作第一PMOS晶体管附近的雪崩注入点。

公开(公告)号：US6020251A

公开(公告)日：2000-02-01

申请号：US63021

申请日：1998-04-20

申请人： Nai-Chen Peng ,  Ming-Tzong Yang

发明人： Nai-Chen Peng ,  Ming-Tzong Yang

IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L21/76202

摘要： A method is provided for use in a semiconductor fabrication process to form buried diffusion junctions in conjunction with shallow-trench isolation (STI) structures in a semiconductor device. This method features beak-like oxide layers formed to serve as a mask prior to the forming of the STI structures, which can prevent the subsequently formed buried diffusion junctions from being broken up during the process for forming the STI structures. Moreover, sidewall-spacer structures are formed on the sidewalls of a silicon nitride layer used as a mask in the ion-implantation process. This can prevent short-circuits between the buried diffusion junctions when the doped areas are annealed to be transformed into the desired buried diffusion junctions.

摘要翻译： 提供了一种在半导体制造工艺中用于在半导体器件中与浅沟槽隔离（STI）结构相结合形成埋入扩散结的方法。 该方法具有形成为在形成STI结构之前用作掩模的喙状氧化物层，这可以防止随后形成的掩埋扩散接头在用于形成STI结构的工艺期间被破坏。 此外，在离子注入工艺中用作掩模的氮化硅层的侧壁上形成侧壁间隔结构。 这可以防止当掺杂区域退火以转化成所需的掩埋扩散结时的掩埋扩散结之间的短路。

公开(公告)号：US20060186455A1

公开(公告)日：2006-08-24

申请号：US10906535

申请日：2005-02-24

申请人： Chien-Hung Chen ,  Nai-Chen Peng ,  Kuang-Pi Lee ,  Tzu-Ping Chen

发明人： Chien-Hung Chen ,  Nai-Chen Peng ,  Kuang-Pi Lee ,  Tzu-Ping Chen

IPC分类号： H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

摘要： A non-volatile memory includes a substrate, a plurality of data storage elements positioned on the substrate, a plurality of control gates positioned above the data storage elements, an insulating layer positioned on surfaces and sidewalls of the control gates, and a bit-line positioned on the insulating layer to cross the control gates.

摘要翻译： 非易失性存储器包括基板，位于基板上的多个数据存储元件，位于数据存储元件上方的多个控制栅极，位于控制栅极的表面和侧壁上的绝缘层，以及位线 位于绝缘层上以跨越控制门。

公开(公告)号：US06291854B1

公开(公告)日：2001-09-18

申请号：US09474997

申请日：1999-12-30

申请人： Nai-Chen Peng

发明人： Nai-Chen Peng

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： A fabrication method for an electrically erasable programmable read only memory is described in which the memory cell has a sharp-cornered polysilicon pillar in junction with the source region to enhance the source side Fowler-Nordheim tunneling effect. The fabrication method sequentially forms an oxide layer and a silicon nitride on a silicon substrate, and then patterns the oxide layer and the silicon nitride layer to form a plurality of trenches. A first doped polysilicon layer is then formed on the substrate and fills the trenches. A wet oxidation is then conducted to grow an oxide layer on the first doped polysilicon layer, from which a sharp-cornered doped polysilicon layer results. A first dielectric layer is further formed on the substrate and the doped polysilicon layer, followed by forming a floating gate on the first dielectric layer. After this, a second dielectric layer is formed on the substrate, covering the floating gate, and a control gate is formed on the second dielectric layer.

摘要翻译： 描述了一种用于电可擦除可编程只读存储器的制造方法，其中存储器单元具有与源极区域连接的锐角多晶硅柱，以增强源极侧的Fowler-Nordheim隧道效应。 制造方法在硅衬底上依次形成氧化物层和氮化硅，然后对氧化物层和氮化硅层进行图案化以形成多个沟槽。 然后在衬底上形成第一掺杂多晶硅层并填充沟槽。 然后进行湿氧化以在第一掺杂多晶硅层上生长氧化物层，从而形成尖锐的掺杂多晶硅层。 在衬底和掺杂多晶硅层上进一步形成第一电介质层，随后在第一电介质层上形成浮栅。 之后，在衬底上形成覆盖浮栅的第二电介质层，在第二电介质层上形成控制栅极。

公开(公告)号：US20060208306A1

公开(公告)日：2006-09-21

申请号：US10907006

申请日：2005-03-16

申请人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

发明人： Nai-Chen Peng ,  Shui-Chin Huang ,  Tzyh-Cheang Lee ,  Chuan Fu Wang ,  Sung-Bin Lin

IPC分类号： H01L29/788

CPC分类号： G11C16/0416 ,  G11C2216/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

摘要： The single-poly EEPROM includes a first PMOS transistor serially connected to a second PMOS transistor. The first and second PMOS transistors are both formed on an N-well of a P type substrate. The first PMOS transistor includes a floating gate, a first P+ doped drain region and a first P+ doped source region. The second PMOS transistor includes a gate and a second P+ doped source region. The first P+ doped drain region of the first PMOS transistor serves as a drain of the second PMOS transistor. A diode is located in the P type substrate including a P-well and a N+ doped region. The floating gate overlaps with the N-well and extends to the N+ doped region. The overlapped region of the P-well and the N+ doped region junction beneath the floating gate serves as an avalanche injection point in the vicinity of the first PMOS transistor.

摘要翻译： 单多晶硅EEPROM包括串联连接到第二PMOS晶体管的第一PMOS晶体管。 第一和第二PMOS晶体管都形成在P型衬底的N阱上。 第一PMOS晶体管包括浮置栅极，第一P + +掺杂漏极区域和第一P + +掺杂源极区域。 第二PMOS晶体管包括栅极和第二P + +掺杂源极区域。 第一PMOS晶体管的第一P + SUP掺杂漏区用作第二PMOS晶体管的漏极。 二极管位于包括P阱和N + +掺杂区的P型衬底中。 浮栅与N阱重叠并延伸到N + +掺杂区。 浮置栅极下面的P阱和N + + / / P>掺杂区域结的重叠区域用作第一PMOS晶体管附近的雪崩注入点。

公开(公告)号：US06878988B1

公开(公告)日：2005-04-12

申请号：US10709854

申请日：2004-06-02

申请人： Tzyh-Cheang Lee ,  Nai-Chen Peng ,  Chungchin Shih ,  Ching-Hung Cheng

发明人： Tzyh-Cheang Lee ,  Nai-Chen Peng ,  Chungchin Shih ,  Ching-Hung Cheng

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/792

摘要： An electrically programmable non-volatile memory cell is provided. A semiconductor substrate is prepared. A pair of spaced apart source/drain (S/D) regions is defined on the semiconductor substrate. The spaced apart S/D regions define a channel region in between. A first dielectric layer such as silicon dioxide is disposed on the S/D regions. An assistant gate is stacked on the first dielectric layer. The assistant gate has a top surface and sidewalls. A second dielectric layer comprising a charge-trapping layer is uniformly disposed on the top surface and sidewalls of the assistant gate and is also disposed on the channel region. The second dielectric layer provides a recessed trough between the S/D regions. A conductive gate material fills the recessed trough for controlling said channel region.

摘要翻译： 提供电可编程的非易失性存储单元。 制备半导体衬底。 在半导体衬底上限定一对间隔开的源极/漏极（S / D）区域。 间隔开的S / D区域在其间限定通道区域。 诸如二氧化硅的第一电介质层设置在S / D区域上。 辅助栅极层叠在第一电介质层上。 辅助门具有顶表面和侧壁。 包括电荷捕获层的第二介电层均匀地设置在辅助栅极的顶表面和侧壁上，并且还设置在沟道区上。 第二电介质层在S / D区域之间提供凹槽。 导电栅极材料填充凹槽以控制所述沟道区域。

公开(公告)号：US6133110A

公开(公告)日：2000-10-17

申请号：US127998

申请日：1998-07-31

申请人： Nai-Chen Peng

发明人： Nai-Chen Peng

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/82 ,  H01L28/92 ,  H01L27/10852

摘要： A method of manufacturing a dual cylinder-shaped capacitor. The method includes the steps of forming a cylindrical oxide layer above a conductive layer, and then forming silicon nitride spacers and first oxide spacers on the sidewalls of the cylindrical oxide layer. Next, using the silicon nitride spacers, the first oxide spacers and the cylindrical oxide layer as a hard mask, the conductive layer is etched to form a separate lower electrode. Thereafter, the oxide layer is removed so that only the silicon nitride spacers remain. Subsequently, second oxide spacers and third oxide spacers are formed on the sidewalls of the silicon nitride spacers. Finally, the silicon nitride spacers are removed, and then the conductive layer is again etched to form the dual cylinder-shaped lower electrode.

摘要翻译： 一种制造双圆柱形电容器的方法。 该方法包括以下步骤：在导电层上形成圆柱形氧化物层，然后在圆柱形氧化物层的侧壁上形成氮化硅间隔物和第一氧化物间隔物。 接下来，使用氮化硅间隔物，第一氧化物间隔物和圆筒形氧化物层作为硬掩模，对导电层进行蚀刻以形成单独的下电极。 此后，去除氧化物层，使得只剩下氮化硅间隔物。 随后，在氮化硅间隔物的侧壁上形成第二氧化物间隔物和第三氧化物间隔物。 最后，去除氮化硅间隔物，然后再次蚀刻导电层以形成双圆柱形下电极。