公开(公告)号：US6140670A

公开(公告)日：2000-10-31

申请号：US128366

申请日：1998-08-03

申请人： Tsun-Tsai Chang

发明人： Tsun-Tsai Chang

IPC分类号： H01L31/103 ,  H01L31/06 ,  H01L29/768

CPC分类号： H01L31/103

摘要： The invention provides a photodiode structure having a first conductive type substrate and at least an isolation region, the photodiode structure comprising a doped second conductive type region, wherein the doped second conductive type region is formed in the substrate at a distance from the neighboring isolation region, and a mask layer covering at least a peripheral strip near the edge of the isolation region so that the doped second conductive type region is exposed.

摘要翻译： 本发明提供一种光电二极管结构，其具有第一导电类型衬底和至少一个隔离区域，所述光电二极管结构包括掺杂的第二导电类型区域，其中所述掺杂的第二导电类型区域形成在距所述相邻隔离区域一定距离的衬底中 以及掩模层，其至少覆盖隔离区域的边缘附近的周边条，使得掺杂的第二导电类型区域露出。

公开(公告)号：US5700711A

公开(公告)日：1997-12-23

申请号：US735222

申请日：1996-10-22

申请人： Chen-Chung Hsu ,  Tsun-Tsai Chang ,  Larry Lin

发明人： Chen-Chung Hsu ,  Tsun-Tsai Chang ,  Larry Lin

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S148/136 ,  Y10S438/926

摘要： A shield structure is formed over each of the undoped or lightly doped polysilicon load devices of a 4T SRAM cell. The shield structure may be a metal such as aluminum, titanium or tungsten and serves to protect the undoped or lightly doped resistor within a polysilicon load device from charge-induced damage during ion implantation or plasma processing steps performed on the SRAM after formation of the polysilicon load device. The polysilicon load device is defined by depositing a layer of photoresist, exposing the photoresist through a master load mask, etching, and implanting into the exposed polysilicon. After the load device is formed, a dielectric layer is deposited and then a layer of conductive material is deposited. Dummy conductor structures are formed from the layer of conductive material using photolithography and the master load mask.

摘要翻译： 在4T SRAM单元的未掺杂或轻掺杂的多晶硅负载器件的每一个上形成屏蔽结构。 屏蔽结构可以是诸如铝，钛或钨的金属，并且用于在多晶硅负载装置内保护未掺杂或轻掺杂的电阻器免受在离子注入期间的电荷引起的损坏或在形成多晶硅之后在SRAM上执行的等离子体处理步骤 负载设备 通过沉积一层光致抗蚀剂来限定多晶硅负载装置，通过主负载掩模曝光光致抗蚀剂，蚀刻和注入暴露的多晶硅。 在形成负载装置之后，沉积介电层，然后沉积一层导电材料。 使用光刻和主负载掩模由导电材料层形成虚拟导体结构。

公开(公告)号：US5576236A

公开(公告)日：1996-11-19

申请号：US496209

申请日：1995-06-28

申请人： Tsun-Tsai Chang ,  Vicent Liu ,  Ming-Tsung Liu

发明人： Tsun-Tsai Chang ,  Vicent Liu ,  Ming-Tsung Liu

IPC分类号： H01L23/544 ,  H01L21/265

CPC分类号： H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： A process for coding and code marking a read-only memory device makes use of a buffer layer, such as silicon nitrides (Si.sub.3 N.sub.4) or silicon oxynitrides (SiN.sub.x O.sub.y), to form a code mark therein. Owing to the etching selectivity between the buffer layer and an underlying layer, for example, silicon oxides, the programmed region not covered by the word lines will not suffer from etching damage while forming the code mark. Therefore, the coding and code marking process can employ the same mask layer, but without the need for two different photomasking procedures to implement code programming and identification code marking.

摘要翻译： 用于对只读存储器件进行编码和代码标记的过程利用诸如氮化硅（Si 3 N 4）或氧氮化硅（SiN x O y）之类的缓冲层在其中形成代码标记。 由于缓冲层和下层之间的蚀刻选择性，例如氧化硅，未被字线覆盖的编程区域在形成代码标记的同时不会遭受蚀刻损伤。 因此，编码和代码标记过程可以采用相同的掩码层，但不需要两个不同的光掩模程序来实现代码编程和识别代码标记。

公开(公告)号：US4902376A

公开(公告)日：1990-02-20

申请号：US290994

申请日：1988-12-28

申请人： Tzer-Perng Chen ,  Yih-Der Guo ,  Tsun-Tsai Chang

发明人： Tzer-Perng Chen ,  Yih-Der Guo ,  Tsun-Tsai Chang

IPC分类号： C30B11/00 ,  C30B29/42 ,  H01L21/208

CPC分类号： C30B11/00 ,  C30B29/42

摘要： A process for growing a gallium arsenide single crystal from a polycrystalline gallium arsenide by the horizontal Bridgman technique includes (a) melting the polycrystalline gallium arsenide in a quartz boat which is placed in a quartz tube, at a temperature greater than 1238 deg C. but lower than the melting point of quartz, (b) decreasing the temperature of the melt of gallium arsenide from the seed/melt interface by moving a furnace to crystallize the melt, and (c) annealing the crystallized gallium arsenide during the crystal growth process at a temperature of 1100-1220 deg C.; wherein the above steps are carried out in the absence of an As vapor pressure controlling zone which is kept at a temperature of about 617 deg C. Due to the anealing step, the thermal stress is small and the dislocation hardly occurs. A short quartz tube can be employed due to the absence of the As zone.

摘要翻译： 通过水平Bridgman技术从多晶砷化镓生长砷化镓单晶的方法包括（a）在高于1238℃的温度下熔化置于石英管中的石英舟中的多晶砷化镓，但是 低于石英的熔点，（b）通过移动炉子使熔融物结晶，从晶种/熔融界面降低砷化镓熔体的温度，和（c）在晶体生长过程中退火结晶的砷化镓 温度为1100-1220摄氏度; 其中上述步骤在没有保持在约617℃温度的As蒸汽压力控制区的情况下进行。由于吸附步骤，热应力小，位错几乎不发生。 由于不存在As区，因此可以使用短的石英管。

公开(公告)号：US5763313A

公开(公告)日：1998-06-09

申请号：US615598

申请日：1996-03-13

申请人： Tsun-Tsai Chang ,  Chen-Chung Hsu

发明人： Tsun-Tsai Chang ,  Chen-Chung Hsu

IPC分类号： H01L21/8244

CPC分类号： H01L27/1112

摘要： A process for fabricating a protective shield for polysilicon loads in SRAM devices is disclosed. The protective shield enables to protect the polyloads from resistance characteristics degradation during the subsequent plasma-based processing steps in the fabrication of the memory device after the polyloads are formed. The polyloads are formed in a photolithography procedure by utilizing a photomask defining the resistive and conductive portions of the polyloads. The process comprises the steps of forming a shield silicon oxide layer over the surface of the memory device in process, including the polyloads, and forming a shield silicon nitride layer on the top of the shield silicon oxide layer. The protective shield is then formed by etching in the shield silicon oxide and nitride layers utilizing a protective photomask. The protective photomask is the same photomask utilized in the formation of the polyloads in the previous photolithography procedural step of the fabrication of the memory device.

摘要翻译： 公开了一种在SRAM器件中制造用于多晶硅负载的保护屏蔽的工艺。 保护屏蔽使得能够在形成多重负载之后在存储器件的制造中随后的基于等离子体的处理步骤期间保护多负载免受电阻特性的降低。 通过利用限定多重负载的电阻和导电部分的光掩模，在光刻工艺中形成多负载。 该方法包括以下步骤：在存储器件的表面上形成屏蔽氧化硅层，包括多重负载，以及在屏蔽氧化硅层的顶部形成屏蔽氮化硅层。 然后通过使用保护光掩模在屏蔽氧化硅和氮化物层中蚀刻形成保护屏蔽。 保护性光掩模是在先前制造存储器件的光刻工艺步骤中用于形成多重负载的相同的光掩模。

公开(公告)号：US5580806A

公开(公告)日：1996-12-03

申请号：US369727

申请日：1995-01-06

申请人： Tsun-Tsai Chang ,  Ming-Tsung Liu

发明人： Tsun-Tsai Chang ,  Ming-Tsung Liu

IPC分类号： H01L21/8244 ,  H01L21/441

CPC分类号： H01L27/11 ,  Y10S148/019

摘要： A buried contact structure formed on a semiconductor substrate. A single polysilicon layer is formed on a field oxide layer. The polysilicon layer is patterned and etched to form an interconnect layer. A silicide layer is formed on the sidewall of the interconnect layer. The silicide layer connects a buried contact region with the interconnect layer to make electrical contact between the interconnect layer and a source/drain region.

摘要翻译： 形成在半导体衬底上的埋入接触结构。 在场氧化物层上形成单个多晶硅层。 对多晶硅层进行图案化和蚀刻以形成互连层。 在互连层的侧壁上形成硅化物层。 硅化物层将掩埋接触区域与互连层连接，以在互连层和源极/漏极区域之间形成电接触。

公开(公告)号：US5952720A

公开(公告)日：1999-09-14

申请号：US851248

申请日：1997-05-05

申请人： Tsun-Tsai Chang

发明人： Tsun-Tsai Chang

IPC分类号： H01L21/74 ,  H01L29/76 ,  H01L27/082 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L21/74 ,  H01L21/76895

摘要： A buried contact structure is provided for forming a contact between a source/drain region of a MOSFET and polysilicon conducting line. The polysilicon conducting line is formed on a field oxide region and extends onto the surface of the semiconductor substrate near the source/drain region. A polysilicon sidewall structure is formed in contact with the vertical edge of the polysilicon conducting line and the horizontal surface of the source/drain region to provide contact between the polysilicon conducting line and the source/drain region.

摘要翻译： 提供掩埋接触结构以形成MOSFET的源/漏区与多晶硅导电线之间的接触。 多晶硅导电线形成在场氧化物区域上并在源/漏区附近延伸到半导体衬底的表面上。 多晶硅侧壁结构形成为与多晶硅导电线的垂直边缘和源极/漏极区域的水平表面接触以提供多晶硅导电线路与源极/漏极区域之间的接触。