公开(公告)号：US20120104603A1

公开(公告)日：2012-05-03

申请号：US13383727

申请日：2010-07-13

申请人： Nitesh Kumbhat ,  Abhishek Choudhury ,  Venky Sundaraman ,  Rao R. Tummala

发明人： Nitesh Kumbhat ,  Abhishek Choudhury ,  Venky Sundaraman ,  Rao R. Tummala

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L24/81 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/75 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/731 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/15788 ,  H05K3/305 ,  H05K3/323 ,  H05K3/3436 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

摘要： The various embodiments of the present invention provide fine pitch, chip-to-substrate interconnect assemblies, as well as methods of making and using the assemblies. The assemblies generally include a semiconductor having a die pad and a bump disposed thereon and a substrate having a substrate pad disposed thereon. The bump is configured to electrically interconnect at least a portion of the semiconductor with at least a portion of the substrate when the bump is contacted with the substrate pad. In addition, when the bump is contacted to the substrate pad, at least a portion of the bump and at least a portion of the substrate pad are deformed so as to create a non-metallurgical bond therebetween.

摘要翻译： 本发明的各种实施例提供细间距，芯片到衬底互连组件，以及制造和使用组件的方法。 组件通常包括具有管芯焊盘和设置在其上的凸块的半导体和其上设置有衬底焊盘的衬底。 凸起构造成当凸块与衬底焊盘接触时将半导体的至少一部分与衬底的至少一部分电互连。 此外，当凸块与衬底焊盘接触时，凸起的至少一部分和衬底焊盘的至少一部分变形，从而在它们之间产生非冶金结合。

公开(公告)号：US20130270695A1

公开(公告)日：2013-10-17

申请号：US13825815

申请日：2011-09-20

申请人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venky Sundaraman ,  Rao R. Tummala ,  Xian Qin

发明人： Pulugurtha Markondeya Raj ,  Nitesh Kumbhat ,  Venky Sundaraman ,  Rao R. Tummala ,  Xian Qin

IPC分类号： H01L23/00

CPC分类号： H01L24/16 ,  H01L24/11 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/181 ,  H05K1/0271 ,  H05K3/3436 ,  H05K3/4007 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00

摘要： The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (μm). The interconnect structure comprises at least a first pad, a supporting pillar, and a solder bump, wherein the first pad and supporting pillar are operative to absorb substantially all plastic strain, therefore enhancing compliance between the two electronic components. The versatility, scalability, and stress-relieving properties of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

摘要翻译： 本发明的各种实施例提供了一种应力消除的二级互连结构，其低成本并且适应低TCE封装和PCB之间的TCE不匹配。 互连结构的各种实施例是可再加工的，并且可以缩放到约1毫米（mm）至约150微米（母体）的间距。 所述互连结构至少包括第一焊盘，支撑柱和焊料凸块，其中所述第一焊盘和支撑柱可操作以吸收基本上所有的塑性应变，从而提高所述两个电子部件之间的顺应性。 本发明的互连结构的多功能性，可扩展性和应力消除特性使其成为在目前的二维和不断发展的三维IC结构中使用的理想结构。