公开(公告)号：US12021066B2

公开(公告)日：2024-06-25

申请号：US17688497

申请日：2022-03-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Fa Lu ,  Cheng-Yuan Tsai ,  Yeur-Luen Tu ,  Chia-Shiung Tsai

IPC分类号： H01L23/498 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H01L27/06

CPC分类号： H01L25/0657 ,  H01L21/76877 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/293 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/562 ,  H01L24/05 ,  H01L24/09 ,  H01L24/13 ,  H01L24/89 ,  H01L25/50 ,  H01L27/0688 ,  H01L21/76805 ,  H01L23/3114 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/023 ,  H01L2224/02351 ,  H01L2224/024 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/80986 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2224/9202 ,  H01L21/76898 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/01029 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/13111 ,  H01L2924/014 ,  H01L2224/13139 ,  H01L2924/014 ,  H01L2224/13147 ,  H01L2924/00014 ,  H01L2224/1145 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11849 ,  H01L2924/00014 ,  H01L2224/9212 ,  H01L2224/80896 ,  H01L2224/8203 ,  H01L2224/821 ,  H01L2224/9212 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2224/05166 ,  H01L2924/01074 ,  H01L2224/80896 ,  H01L2924/00012

摘要： A structure includes first and second substrates, first and second stress buffer layers, and a post-passivation interconnect (PPI) structure. The first and second substrates include first and second semiconductor substrates and first and second interconnect structures on the first and second semiconductor substrates, respectively. The second interconnect structure is on a first side of the second semiconductor substrate. The first substrate is bonded to the second substrate at a bonding interface. A via extends at least through the second semiconductor substrate into the second interconnect structure. The first stress buffer layer is on a second side of the second semiconductor substrate opposite from the first side of the second semiconductor substrate. The PPI structure is on the first stress buffer layer and is electrically coupled to the via. The second stress buffer layer is on the PPI structure and the first stress buffer layer.

公开(公告)号：US11664335B2

公开(公告)日：2023-05-30

申请号：US15358038

申请日：2016-11-21

申请人： Semikron Elektronik GmbH & Co., KG

发明人： Wolfgang-Michael Schulz

IPC分类号： H01L23/00 ,  H01L23/488

CPC分类号： H01L24/05 ,  H01L23/488 ,  H01L24/03 ,  H01L24/08 ,  H01L24/48 ,  H01L24/85 ,  H01L24/45 ,  H01L2224/0345 ,  H01L2224/0347 ,  H01L2224/03462 ,  H01L2224/03823 ,  H01L2224/04042 ,  H01L2224/05005 ,  H01L2224/0508 ,  H01L2224/0516 ,  H01L2224/05023 ,  H01L2224/0558 ,  H01L2224/0566 ,  H01L2224/05118 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05583 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05679 ,  H01L2224/05684 ,  H01L2224/08503 ,  H01L2224/45005 ,  H01L2224/45015 ,  H01L2224/4554 ,  H01L2224/45147 ,  H01L2224/4847 ,  H01L2224/48247 ,  H01L2224/48506 ,  H01L2224/48507 ,  H01L2224/48855 ,  H01L2224/85205 ,  H01L2224/85375 ,  H01L2924/00014 ,  H01L2224/45147 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/2076 ,  H01L2224/05171 ,  H01L2924/00014 ,  H01L2224/05179 ,  H01L2924/00014 ,  H01L2224/05172 ,  H01L2924/00014 ,  H01L2224/05147 ,  H01L2924/00014 ,  H01L2224/05139 ,  H01L2924/00014 ,  H01L2224/05164 ,  H01L2924/00014 ,  H01L2224/0516 ,  H01L2924/00014 ,  H01L2224/05118 ,  H01L2924/00014 ,  H01L2224/05155 ,  H01L2924/00014 ,  H01L2224/05664 ,  H01L2924/00014 ,  H01L2224/05166 ,  H01L2924/00014 ,  H01L2224/05184 ,  H01L2924/00014 ,  H01L2224/05186 ,  H01L2924/01074 ,  H01L2224/05186 ,  H01L2924/01022 ,  H01L2224/45005 ,  H01L2924/2076 ,  H01L2224/45147 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/00014 ,  H01L2224/43848 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2924/013 ,  H01L2924/01014

摘要： A power semiconductor chip having: a semiconductor component body; a multilayer metallization arranged on the semiconductor component body; and a nickel layer arranged over the semiconductor component body. The invention further relates to a method for producing a power semiconductor chip and to a power semiconductor device. The invention provides a power semiconductor chip which has a metallization to which a copper wire, provided without a thick metallic coating, can be reliably bonded without damage to the power semiconductor chip during bonding.

公开(公告)号：US20180040577A1

公开(公告)日：2018-02-08

申请号：US15667610

申请日：2017-08-02

申请人： Dyi-Chung HU

发明人： Dyi-Chung HU

IPC分类号： H01L23/00

CPC分类号： H01L24/06 ,  H01L23/498 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03602 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16111 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014

摘要： A pad structure adapted to be disposed on a first package substrate and electrically connected to conductive contacts of a second package substrate includes a first conductive pad having a first top surface, a second conductive pad, a first leveling conductor and a second leveling conductor is provided. The second conductive pad disposed aside the first conductive pad has a second top surface non-coplanar with the first top surface. The first leveling conductor disposed on the first conductive pad has a first leveling surface opposite to the first top surface. The second leveling conductor disposed on the second conductive pad and having a second leveling surface opposite to the second top surface is coplanar with the first leveling surface. The conductive contacts of the second package substrate are disposed on the first leveling conductor and the second leveling conductor. A manufacturing method of a pad structure is also provided.

公开(公告)号：US09865524B2

公开(公告)日：2018-01-09

申请号：US14222547

申请日：2014-03-21

申请人： STATS ChipPAC, Ltd.

发明人： Duk Ju Na ,  Chang Beom Yong ,  Pandi C. Marimuthu

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/31 ,  H01L21/66

CPC分类号： H01L23/481 ,  H01L21/76898 ,  H01L22/12 ,  H01L22/14 ,  H01L23/3171 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L2224/03002 ,  H01L2224/03009 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05027 ,  H01L2224/05558 ,  H01L2224/0557 ,  H01L2224/0558 ,  H01L2224/05584 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/05671 ,  H01L2224/05684 ,  H01L2224/06181 ,  H01L2224/11002 ,  H01L2224/11009 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01023 ,  H01L2924/01074 ,  H01L2924/01029 ,  H01L2924/00 ,  H01L2224/05552

摘要： A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.

公开(公告)号：US20170271242A1

公开(公告)日：2017-09-21

申请号：US15614339

申请日：2017-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L21/288 ,  H01L23/525

CPC分类号： H01L23/481 ,  H01L21/2885 ,  H01L21/76847 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L29/43 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05005 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/207

摘要： An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

公开(公告)号：US20170250172A1

公开(公告)日：2017-08-31

申请号：US15431528

申请日：2017-02-13

申请人： Semtech Corporation

发明人： Changjun Huang ,  Jonathan Clark

IPC分类号： H01L25/00 ,  H01L27/02 ,  H01L23/00 ,  H01L21/78 ,  H01L25/065 ,  H01L21/768

CPC分类号： H01L25/50 ,  H01L21/304 ,  H01L21/561 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3171 ,  H01L23/49575 ,  H01L23/60 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/85 ,  H01L24/94 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/0255 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/08146 ,  H01L2224/08148 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/17181 ,  H01L2224/2929 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/48465 ,  H01L2224/4847 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/80203 ,  H01L2224/8082 ,  H01L2224/80895 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10324 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/1203 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/01082 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/81 ,  H01L2224/80 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device has a first semiconductor die including a first protection circuit. A second semiconductor die including a second protection circuit is disposed over the first semiconductor die. A portion of the first semiconductor die and second semiconductor die is removed to reduce die thickness. An interconnect structure is formed to commonly connect the first protection circuit and second protection circuit. A transient condition incident to the interconnect structure is collectively discharged through the first protection circuit and second protection circuit. Any number of semiconductor die with protection circuits can be stacked and interconnected via the interconnect structure to increase the ESD current discharge capability. The die stacking can be achieved by disposing a first semiconductor wafer over a second semiconductor wafer and then singulating the wafers. Alternatively, die-to-wafer or die-to-die assembly is used.

公开(公告)号：US09673132B2

公开(公告)日：2017-06-06

申请号：US14511006

申请日：2014-10-09

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiao Yun Lo ,  Yung-Chi Lin ,  Yang-Chih Hsueh ,  Tsang-Jiuh Wu ,  Wen-Chih Chiou

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L23/532 ,  H01L21/288 ,  H01L23/525

CPC分类号： H01L23/481 ,  H01L21/2885 ,  H01L21/7685 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/525 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53242 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05005 ,  H01L2224/05018 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05026 ,  H01L2224/05099 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/0518 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05541 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/0558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/0568 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/1131 ,  H01L2224/1134 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/00012 ,  H01L2924/207 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2224/81805

摘要： An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic variations. The interconnection structure includes a contact pad disposed over a substrate. The contact pad includes a first layer of a first conductive material and a second layer of a second conductive material over the first layer. The first conductive material and the second conductive material are made of substantially the same material and have a first average grain size and a second average grain size that is smaller than the first average grain size. The interconnection structure also includes a passivation layer covering the substrate and the contact pad, and the passivation layer has an opening exposing the contact pad.

公开(公告)号：US09607954B2

公开(公告)日：2017-03-28

申请号：US15154954

申请日：2016-05-14

申请人： Renesas Electronics Corporation

发明人： Akira Yajima

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L24/02 ,  G11C29/06 ,  G11C29/50016 ,  G11C29/56016 ,  G11C2029/0403 ,  G11C2029/5602 ,  H01L22/14 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/92 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/03831 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/0558 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/119 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/92 ,  H01L2224/94 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/01028 ,  H01L2924/00014 ,  H01L2224/0231 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/03848 ,  H01L22/10 ,  H01L22/12 ,  H01L21/78 ,  H01L2924/00012

摘要： Object is to prevent a coupling failure between a rewiring and a coupling member for coupling to outside. A passivation film and a first polyimide film are formed so as to cover a wiring layer. A first opening portion is formed in the first polyimide film. A rewiring is formed on the first polyimide film so as to be coupled to the wiring layer via the first opening portion. A second polyimide film that covers the rewiring and has a second opening portion communicated with the rewiring is formed. A palladium film is formed as a barrier film by sputtering on a portion of the surface of the rewiring at which the second opening portion exists. A solder ball is coupled to the palladium film.

公开(公告)号：US09607949B2

公开(公告)日：2017-03-28

申请号：US14641864

申请日：2015-03-09

申请人： Kabushiki Kaisha Toshiba

发明人： Hiroshi Yamada

IPC分类号： H01L25/065 ,  H01L23/538 ,  H01L23/31 ,  H01L23/04 ,  H01L23/00 ,  H01L23/29 ,  H01L23/433 ,  H01L23/36 ,  H01L23/498 ,  H01L21/56

CPC分类号： H01L23/5386 ,  H01L21/568 ,  H01L23/295 ,  H01L23/36 ,  H01L23/4334 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L25/0652 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05568 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/12105 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13184 ,  H01L2224/1403 ,  H01L2224/14135 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/1424 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/11

摘要： A semiconductor device includes a first semiconductor unit including a plurality of first semiconductor chips, an organic resin provided between the first semiconductor chips, a wiring layer provided above the first semiconductor chips to electrically connect the first semiconductor chips to each other, and a plurality of connecting terminals provided on an upper portion of the wiring layer and a second semiconductor unit fixed to a wiring layer side of the first semiconductor unit, the second semiconductor unit fixed to a region sandwiched between the connecting terminals, the second semiconductor unit having a second semiconductor chip, the second semiconductor unit electrically connected to the first semiconductor unit.

公开(公告)号：US20170084577A1

公开(公告)日：2017-03-23

申请号：US15364715

申请日：2016-11-30

申请人： SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

发明人： Francis J. CARNEY ,  Michael J. SEDDON

IPC分类号： H01L25/065 ,  H01L21/768 ,  H01L21/48 ,  H01L25/00

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L21/76877 ,  H01L23/13 ,  H01L23/49805 ,  H01L24/05 ,  H01L24/08 ,  H01L24/16 ,  H01L24/24 ,  H01L24/25 ,  H01L24/73 ,  H01L24/80 ,  H01L24/81 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05557 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/06181 ,  H01L2224/06183 ,  H01L2224/08137 ,  H01L2224/11002 ,  H01L2224/14181 ,  H01L2224/14183 ,  H01L2224/16137 ,  H01L2224/16147 ,  H01L2224/24051 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/29019 ,  H01L2224/29021 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/30151 ,  H01L2224/32137 ,  H01L2224/73251 ,  H01L2224/73267 ,  H01L2224/80897 ,  H01L2224/809 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2224/81897 ,  H01L2224/821 ,  H01L2224/82121 ,  H01L2224/82138 ,  H01L2224/82203 ,  H01L2224/82815 ,  H01L2224/82862 ,  H01L2224/82874 ,  H01L2224/83141 ,  H01L2224/83203 ,  H01L2224/839 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06551 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/10156 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10322 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/15159 ,  H01L2924/19104 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/03 ,  H05K3/4661 ,  H05K3/4664 ,  H01L2924/00014 ,  H01L2224/80001 ,  H01L2224/82 ,  H01L2924/00012 ,  H01L2224/08 ,  H01L2224/24 ,  H01L2224/83 ,  H01L2924/014

摘要： A semiconductor device has a plurality of interconnected modular units to form a 3D semiconductor package. Each modular unit is implemented as a vertical component or a horizontal component. The modular units are interconnected through a vertical conduction path and lateral conduction path within the vertical component or horizontal component. The vertical component and horizontal component each have an interconnect interposer or semiconductor die. A first conductive via is formed vertically through the interconnect interposer. A second conductive via is formed laterally through the interconnect interposer. The interconnect interposer can be programmable. A plurality of protrusions and recesses are formed on the vertical component or horizontal component, and a plurality of recesses on the vertical component or horizontal component. The protrusions are inserted into the recesses to interlock the vertical component and horizontal component. The 3D semiconductor package can be formed with multiple tiers of vertical components and horizontal components.