公开(公告)号：US07398444B2

公开(公告)日：2008-07-08

申请号：US11220332

申请日：2005-09-06

申请人： Martin Brox ,  Robert Kaiser ,  Volker Kilian ,  Wolfgang Spirkl

发明人： Martin Brox ,  Robert Kaiser ,  Volker Kilian ,  Wolfgang Spirkl

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31716 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50 ,  G11C29/50012

摘要： The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.

摘要翻译： 本发明涉及一种用于测试存储器件的方法，该存储器件能够以正常操作模式和测试模式操作并且包含输出驱动器，输入驱动器和数据焊盘。 该方法包括以下步骤：将用于测试的测试输入数据传送到存储器件，使用测试输入数据执行测试，以便获得测试输出数据，读出的测试数据经由输出驱动器通过， 至少一个数据焊盘和输入驱动器，其中在测试期间切换输入驱动器和输出驱动器，使得能够同时从存储器件读取和写入数据，并且从 测试输出数据。 此外，本发明涉及用于测试存储器件的存储器件和系统。

公开(公告)号：US06600331B2

公开(公告)日：2003-07-29

申请号：US10158271

申请日：2002-05-30

申请人： Volker Kilian ,  Richard Roth

发明人： Volker Kilian ,  Richard Roth

IPC分类号： G01R3102

CPC分类号： G01K7/01

摘要： The invention relates to a method for measuring the junction temperature in an electronic component. A periodic test signal is led via a signal path inside the component in order to obtain an internal signal. There is a frequency and/or phase relationship between the periodic test signal and a periodic external signal. A phase shift is measured between the internal signal and the external signal. The junction temperature is determined over the component region determined by the signal path as a function of the phase shift.

公开(公告)号：US07349253B2

公开(公告)日：2008-03-25

申请号：US11343357

申请日：2006-01-31

申请人： Martin Perner ,  Volker Kilian

发明人： Martin Perner ,  Volker Kilian

IPC分类号： G11C11/34

CPC分类号： G11C29/846

摘要： A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same loads during manufacturing and test processes, and that at least one regular memory cell from a regular memory area and at least one redundant memory cell from a redundant memory area are connected with each other via a coupling circuit. The coupling circuit, in particular during the testing of the operability of the semiconductor memory device or of the memory cells, respectively, determines the state of the regular memory cell and/or the redundant memory cell. Thus, in tested and repaired semiconductor memory devices, so-called redundancy storage space for the repair of defective memory capacity can be provided for repair even in the last memory test step, including full test severity and fulfilling all and any reliability requirements for the repair of high-grade memory devices.

摘要翻译： 公开了一种用于测试具有可修复冗余的存储器件的存储器件和方法。 在一个实施例中，常规存储器区域和冗余存储器区域在制造和测试过程期间受到相同的负载，并且来自常规存储器区域的至少一个常规存储器单元和来自冗余存储器的至少一个冗余存储器单元 区域通过耦合电路彼此连接。 特别是在测试半导体存储器件或存储器单元的可操作性期间，耦合电路分别确定常规存储单元和/或冗余存储单元的状态。 因此，在测试和修复的半导体存储器件中，即使在最后的存储器测试步骤中也可以提供用于修复缺陷存储器容量的所谓的冗余存储空间，包括完整的测试严重性并满足修复的所有和任何可靠性要求 的高档记忆体装置。

公开(公告)号：US07184339B2

公开(公告)日：2007-02-27

申请号：US11253807

申请日：2005-10-20

申请人： Thorsten Bucksch ,  Martin Perner ,  Volker Kilian ,  Martin Meier

发明人： Thorsten Bucksch ,  Martin Perner ,  Volker Kilian ,  Martin Meier

IPC分类号： G11C29/00

CPC分类号： G11C29/1201 ,  G11C29/48 ,  G11C2029/1208 ,  G11C2029/1806

摘要： The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data into or from a semi-conductor component, whereby the semi-conductor component comprises one or more useful data memory cells, and/or one or more test data and/or semi-conductor component operating control data registers for storing test data and/or semi-conductor component operating control data, and whereby the process comprises the steps of applying a control signal to the semi-conductor component, whereby the semi-conductor component is switched from a first to a second operating mode; and applying an address signal to the semi-conductor component, whereby one or more of the test data and/or semi-conductor component operating control data registers of the semi-conductor component is addressed by the address signal in the second operating mode, and one or more of the useful data memory cells in the first operating mode.

摘要翻译： 本发明涉及一种半导体部件，以及用于将测试数据和/或半导体部件输入和/或输出到半导体部件中或从半导体部件操作控制数据的过程，由此半导体部件包括 一个或多个有用的数据存储器单元，和/或用于存储测试数据和/或半导体部件操作控制数据的一个或多个测试数据和/或半导体部件操作控制数据寄存器，并且由此该过程包括以下步骤： 对半导体部件施加控制信号，由此将半导体部件从第一操作模式切换到第二操作模式; 以及向所述半导体部件施加地址信号，由此所述半导体部件的测试数据和/或半导体部件操作控制数据寄存器中的一个或多个通过所述第二操作模式中的所述地址信号来寻址，以及 处于第一操作模式的一个或多个有用数据存储单元。

公开(公告)号：US20060198215A1

公开(公告)日：2006-09-07

申请号：US11343357

申请日：2006-01-31

申请人： Martin Perner ,  Volker Kilian

发明人： Martin Perner ,  Volker Kilian

IPC分类号： G11C29/00

CPC分类号： G11C29/846

摘要： A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same loads during manufacturing and test processes, and that at least one regular memory cell from a regular memory area and at least one redundant memory cell from a redundant memory area are connected with each other via a coupling circuit. The coupling circuit, in particular during the testing of the operability of the semiconductor memory device or of the memory cells, respectively, determines the state of the regular memory cell and/or the redundant memory cell. Thus, in tested and repaired semiconductor memory devices, so-called redundancy storage space for the repair of defective memory capacity can be provided for repair even in the last memory test step, including full test severity and fulfilling all and any reliability requirements for the repair of high-grade memory devices.

摘要翻译： 公开了一种用于测试具有可修复冗余的存储器件的存储器件和方法。 在一个实施例中，常规存储器区域和冗余存储器区域在制造和测试过程期间受到相同的负载，并且来自常规存储器区域的至少一个常规存储器单元和来自冗余存储器的至少一个冗余存储器单元 区域通过耦合电路彼此连接。 特别是在测试半导体存储器件或存储器单元的可操作性期间，耦合电路分别确定常规存储单元和/或冗余存储单元的状态。 因此，在测试和修复的半导体存储器件中，即使在最后的存储器测试步骤中也可以提供用于修复缺陷存储器容量的所谓的冗余存储空间，包括完整的测试严重性并满足修复的所有和任何可靠性要求 的高档记忆体装置。

公开(公告)号：US20060087900A1

公开(公告)日：2006-04-27

申请号：US11253807

申请日：2005-10-20

申请人： Thorsten Bucksch ,  Martin Perner ,  Volker Kilian ,  Martin Meier

发明人： Thorsten Bucksch ,  Martin Perner ,  Volker Kilian ,  Martin Meier

IPC分类号： G11C7/00

CPC分类号： G11C29/1201 ,  G11C29/48 ,  G11C2029/1208 ,  G11C2029/1806

摘要： The invention relates to a semi-conductor component, and a process for the in- and/or output of test data and/or semi-conductor component operating control data into or from a semi-conductor component, whereby the semi-conductor component comprises one or more useful data memory cells, and/or one or more test data and/or semi-conductor component operating control data registers for storing test data and/or semi-conductor component operating control data, and whereby the process comprises the steps of applying a control signal to the semi-conductor component, whereby the semi-conductor component is switched from a first to a second operating mode; and applying an address signal to the semi-conductor component, whereby one or more of the test data and/or semi-conductor component operating control data registers of the semi-conductor component is addressed by the address signal in the second operating mode, and one or more of the useful data memory cells in the first operating mode.

摘要翻译： 本发明涉及一种半导体部件，以及用于将测试数据和/或半导体部件输入和/或输出到半导体部件中或从半导体部件操作控制数据的过程，由此半导体部件包括 一个或多个有用的数据存储器单元，和/或用于存储测试数据和/或半导体部件操作控制数据的一个或多个测试数据和/或半导体部件操作控制数据寄存器，并且由此该过程包括以下步骤： 对半导体部件施加控制信号，由此将半导体部件从第一操作模式切换到第二操作模式; 以及向所述半导体部件施加地址信号，由此所述半导体部件的测试数据和/或半导体部件操作控制数据寄存器中的一个或多个通过所述第二操作模式中的地址信号来寻址，以及 处于第一操作模式的一个或多个有用数据存储单元。

公开(公告)号：US20060059397A1

公开(公告)日：2006-03-16

申请号：US11220332

申请日：2005-09-06

申请人： Martin Brox ,  Robert Kaiser ,  Volker Kilian ,  Wolfgang Spirkl

发明人： Martin Brox ,  Robert Kaiser ,  Volker Kilian ,  Wolfgang Spirkl

IPC分类号： G06F11/00 ,  G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31716 ,  G11C29/02 ,  G11C29/022 ,  G11C29/50 ,  G11C29/50012

摘要： The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and comprising output driver, input driver, and data pads. The method comprises the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.

摘要翻译： 本发明涉及一种用于测试存储器件的方法，该存储器件能够以正常操作模式和测试模式操作并且包括输出驱动器，输入驱动器和数据焊盘。 该方法包括以下步骤：将用于测试的测试输入数据传送到存储器件，使用测试输入数据执行测试，以便获得测试输出数据，读出的测试数据经由输出驱动器通过， 至少一个数据焊盘和输入驱动器，其中在测试期间切换输入驱动器和输出驱动器，使得能够同时从存储器件读取和写入数据，并且从 测试输出数据。 此外，本发明涉及用于测试存储器件的存储器件和系统。

公开(公告)号：US06870392B2

公开(公告)日：2005-03-22

申请号：US10368330

申请日：2003-02-18

申请人： Volker Kilian ,  Richard Roth

发明人： Volker Kilian ,  Richard Roth

IPC分类号： G01R31/319 ,  G11C29/36 ,  H03K19/173

CPC分类号： G11C29/36 ,  G01R31/31922

摘要： To generate test signals by a test logic unit on a semiconductor wafer, the test signals being used to check specific functions and/or parameters of an integrated circuit on the semiconductor wafer, at least two test signals are provided substantially simultaneously by the test logic unit and are subsequently serialized to generate a multiplexed test signal sequence with a data rate required for testing.

摘要翻译： 为了通过半导体晶片上的测试逻辑单元生成测试信号，测试信号用于检查半导体晶片上的集成电路的特定功能和/或参数，至少两个测试信号基本上由测试逻辑单元 并随后串行化以产生具有测试所需的数据速率的复用测试信号序列。

公开(公告)号：US07113015B2

公开(公告)日：2006-09-26

申请号：US10291069

申请日：2002-11-08

申请人： Lenart Hauptner ,  Volker Kilian ,  Richard Roth ,  Stefan Sommer

发明人： Lenart Hauptner ,  Volker Kilian ,  Richard Roth ,  Stefan Sommer

IPC分类号： H03H11/26

CPC分类号： G11C11/4076 ,  G11C7/22 ,  G11C2207/2254

摘要： A tuning circuit for setting a signal propagation time on a signal line in an integrated circuit, particularly a DRAM circuit, has a transistor and a capacitor. A control connection of the transistor is connected to a control unit for the purpose of switchably connecting the capacitor to the signal line through the transistor in order to set the signal propagation time on the signal line on the basis of application of a control signal, generated in the control unit, to the control connection on the transistor.

公开(公告)号：US06867597B2

公开(公告)日：2005-03-15

申请号：US10292847

申请日：2002-11-12

申请人： Lenart Hauptner ,  Volker Kilian ,  Richard Roth ,  Stefan Sommer

发明人： Lenart Hauptner ,  Volker Kilian ,  Richard Roth ,  Stefan Sommer

IPC分类号： G01R31/28 ,  G01R31/11

CPC分类号： G01R31/2812

摘要： In the case of the present-day trend of miniaturizing housed electronic devices, there is the problem that the contact spacings between the terminal pins becomes smaller and smaller and are no longer visible optically. As a result, it also becomes more difficult to solder the contacts of correspondingly designed contact bases, which for example, are designed as test bases, to the individual conductor tracks of the printed circuit board. Possible faulty soldering points, short circuits or interruptions have hitherto been tracked down by laborious manual measurement using the TDR method. The invention proposes producing a test device in which in each case two terminal pins are connected to a short-circuiting bridge. The test device is inserted into the contact base and connects two signal paths of the printed circuit board on which the propagation time of a reflected wave can be measured.

摘要翻译： 在目前电子设备小型化趋势的情况下，存在端子引脚之间的接触间距变得越来越小并且在光学上不再可见的问题。 结果，将相应设计的接触基底（例如被设计为测试基座）的触点焊接到印刷电路板的各个导体轨迹上变得更加困难。 迄今为止，通过使用TDR方法进行了费力的手动测量，可能会导致焊接点，短路或中断故障。 本发明提出一种测试装置，其中在每种情况下两个端子引脚连接到短路桥。 将测试装置插入到接触基底中，并连接能够测量反射波的传播时间的印刷电路板的两个信号路径。