公开(公告)号：US07675062B2

公开(公告)日：2010-03-09

申请号：US11455367

申请日：2006-06-19

申请人： Mun-Pyo Hong ,  Wan-Shick Hong ,  Sang-Il Kim ,  Soo-Guy Rho ,  Jin-Kyu Kang ,  Snag-Gab Kim

发明人： Mun-Pyo Hong ,  Wan-Shick Hong ,  Sang-Il Kim ,  Soo-Guy Rho ,  Jin-Kyu Kang ,  Snag-Gab Kim

IPC分类号： H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20

CPC分类号： G02F1/136227 ,  G02F1/136209 ,  G02F1/136286 ,  G02F2001/136222 ,  H01L27/12 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908

摘要： A black matrix having an opening at pixels of a matrix array in a display area, a common wire including common pads and common signal lines, and gate pads in a peripheral area, and an alignment key in outer area to align interlayer thin films are formed on an insulating substrate. Red, blue and green color filters the edge of which overlap the black matrix are formed at the pixels on the insulating substrate, and an organic insulating layer covering the black matrix and the color filters and having a contact hole exposing the gate pad is formed thereon. A gate wire including a gate line connected to the gate pad through the contact hole and a gate electrode connected to the gate line is formed on the organic insulating layer, and a gate insulating layer covering the gate wire is formed on the organic insulating layer. A semiconductor pattern and ohmic contact layers are sequentially formed on the gate insulating layer of the gate electrode. A data wire including a source electrode and a drain electrode that are made of a same layer on the ohmic contact layers and separated from each other, and a data line connected to the source electrode and defining the pixels of a matrix array by crossing the gate line is formed on the gate insulating layer. A passivation layer covering the data wire and having contact holes exposing the gate pad and the data pad is formed, and a pixel wire including a pixel electrode, a redundant gate pad, a redundant data pad that are respectively connected to the drain electrode, the gate pad and the data pad through the contact holes.

摘要翻译： 形成在显示区域中具有矩阵阵列的像素的开口的黑矩阵，包括公共焊盘和公共信号线的公共线，以及外围区域中的栅极焊盘以及外部区域中的对准键来对准层间薄膜 在绝缘基板上。 在绝缘基板上的像素处形成与黑矩阵重叠的边缘的红色，蓝色和绿色滤色片，并且在其上形成覆盖黑矩阵和滤色器并且具有暴露栅极接触孔的接触孔的有机绝缘层 。 在有机绝缘层上形成包括通过接触孔连接到栅极焊盘的栅极线和连接到栅极线的栅极的栅极线，并且在有机绝缘层上形成覆盖栅极线的栅极绝缘层。 半导体图案和欧姆接触层依次形成在栅电极的栅极绝缘层上。 一种数据线，包括在欧姆接触层上由相同层制成并彼此分离的源电极和漏电极，以及连接到源电极并通过跨越栅极定义矩阵阵列的像素的数据线 线形成在栅极绝缘层上。 形成覆盖数据线并具有露出栅极焊盘和数据焊盘的接触孔的钝化层，并且包括分别连接到漏电极的像素电极，冗余栅极焊盘，冗余数据焊盘的像素线， 栅极焊盘和数据焊盘通过接触孔。

公开(公告)号：US07358104B2

公开(公告)日：2008-04-15

申请号：US11359138

申请日：2006-02-22

申请人： Bo Sung Kim ,  Kwan-Wook Jung ,  Wan-Shick Hong ,  Sang-Gab Kim ,  Mun-Pyo Hong

发明人： Bo Sung Kim ,  Kwan-Wook Jung ,  Wan-Shick Hong ,  Sang-Gab Kim ,  Mun-Pyo Hong

IPC分类号： H01L21/00

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288

摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mas, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the firs wire via the contact holes.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔 使用感光膜作为蚀刻的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界，并且形成通过接触孔连接到第一线的第二线。

公开(公告)号：US07190421B2

公开(公告)日：2007-03-13

申请号：US10660749

申请日：2003-09-12

申请人： Mun-Pyo Hong ,  Wan-Shick Hong ,  Sang-Il Kim ,  Soo-Guy Rho ,  Jin-Kyu Kang ,  Snag-Gab Kim

发明人： Mun-Pyo Hong ,  Wan-Shick Hong ,  Sang-Il Kim ,  Soo-Guy Rho ,  Jin-Kyu Kang ,  Snag-Gab Kim

IPC分类号： G02F1/136 ,  G02F1/1335 ,  G02F1/1333

CPC分类号： G02F1/136227 ,  G02F1/136209 ,  G02F1/136286 ,  G02F2001/136222 ,  H01L27/12 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908

摘要： A black matrix having an opening at pixels of a matrix array in a display area, a common wire including common pads and common signal lines, and gate pads in a peripheral area, and an alignment key in outer area to align interlayer thin films are formed on an insulating substrate. Red, blue and green color filters the edge of which overlap the black matrix are formed at the pixels on the insulating substrate, and an organic insulating layer covering the black matrix and the color filters and having a contact hole exposing the gate pad is formed thereon. A gate wire including a gate line connected to the gate pad through the contact hole and a gate electrode connected to the gate line is formed on the organic insulating layer, and a gate insulating layer covering the gate wire is formed on the organic insulating layer. A semiconductor pattern and ohmic contact layers are sequentially formed on the gate insulating layer of the gate electrode. A data wire including a source electrode and a drain electrode that are made of a same layer on the ohmic contact layers and separated from each other, and a data line connected to the source electrode and defining the pixels of a matrix array by crossing the gate line is formed on the gate insulating layer. A passivation layer covering the data wire and having contact holes exposing the gate pad and the data pad is formed, and a pixel wire including a pixel electrode, a redundant gate pad, a redundant data pad that are respectively connected to the drain electrode, the gate pad and the data pad through the contact holes.

摘要翻译： 形成在显示区域中具有矩阵阵列的像素的开口的黑矩阵，包括公共焊盘和公共信号线的公共线，以及外围区域中的栅极焊盘以及外部区域中的对准键来对准层间薄膜 在绝缘基板上。 在绝缘基板上的像素处形成与黑矩阵重叠的边缘的红色，蓝色和绿色滤色片，并且在其上形成覆盖黑矩阵和滤色器并且具有暴露栅极接触孔的接触孔的有机绝缘层 。 在有机绝缘层上形成包括通过接触孔连接到栅极焊盘的栅极线和连接到栅极线的栅极的栅极线，并且在有机绝缘层上形成覆盖栅极线的栅极绝缘层。 半导体图案和欧姆接触层依次形成在栅电极的栅极绝缘层上。 一种数据线，包括在欧姆接触层上由相同层制成并彼此分离的源电极和漏电极，以及连接到源电极并通过跨越栅极定义矩阵阵列的像素的数据线 线形成在栅极绝缘层上。 形成覆盖数据线并具有露出栅极焊盘和数据焊盘的接触孔的钝化层，并且包括分别连接到漏电极的像素电极，冗余栅极焊盘，冗余数据焊盘的像素线， 栅极焊盘和数据焊盘通过接触孔。

公开(公告)号：US20060138424A1

公开(公告)日：2006-06-29

申请号：US11359138

申请日：2006-02-22

申请人： Bo Sung Kim ,  Kwan-Wook Jung ,  Wan-Shick Hong ,  Sang-Gab Kim ,  Mun-Pyo Hong

发明人： Bo Sung Kim ,  Kwan-Wook Jung ,  Wan-Shick Hong ,  Sang-Gab Kim ,  Mun-Pyo Hong

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288

摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mas, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the firs wire via the contact holes.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔 使用感光膜作为蚀刻的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界，并且形成通过接触孔连接到第一线的第二线。

公开(公告)号：US20050148143A1

公开(公告)日：2005-07-07

申请号：US11071544

申请日：2005-03-03

申请人： Sung-Hoon Yang ,  Wan-Shick Hong ,  Kwan-Wook Jung

发明人： Sung-Hoon Yang ,  Wan-Shick Hong ,  Kwan-Wook Jung

IPC分类号： G02F1/1368 ,  C23C16/30 ,  C23C16/42 ,  G02F1/1362 ,  H01L21/205 ,  H01L21/312 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  H01L51/56

CPC分类号： G02F1/136227 ,  C23C16/30 ,  G02F2001/136222 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/458 ,  H01L29/4908 ,  H01L51/56

摘要： The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

摘要翻译： 本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用其的薄膜晶体管及其制备方法，更具体地涉及可以显着改善蒸气的低介电绝缘膜的气相沉积方法 同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成 用于半导体器件的保护膜。 本发明还涉及使用该方法及其制备方法的薄膜晶体管。

公开(公告)号：US07737445B2

公开(公告)日：2010-06-15

申请号：US12030992

申请日：2008-02-14

申请人： Bo Sung Kim ,  Kwan-Wook Jung ,  Wan-Shick Hong ,  Sang-Gab Kim ,  Mun-Pyo Hong

发明人： Bo Sung Kim ,  Kwan-Wook Jung ,  Wan-Shick Hong ,  Sang-Gab Kim ,  Mun-Pyo Hong

IPC分类号： H01L29/04

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288

摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mask, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the first wire via the contact holes.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔 使用感光膜作为蚀刻掩模的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界线，并且经由接触孔形成连接到第一线的第二线。

公开(公告)号：US07615783B2

公开(公告)日：2009-11-10

申请号：US11436073

申请日：2006-05-17

申请人： Joon-Hoo Choi ,  Wan-Shick Hong ,  Dae-Jin Kwon ,  Kwan-Wook Jung ,  Sang-Gab Kim ,  Kyu-Ha Jung

发明人： Joon-Hoo Choi ,  Wan-Shick Hong ,  Dae-Jin Kwon ,  Kwan-Wook Jung ,  Sang-Gab Kim ,  Kyu-Ha Jung

IPC分类号： H01L51/30

CPC分类号： H01L29/66765 ,  G02F1/136227 ,  G02F2001/133357 ,  G02F2001/136236 ,  H01L27/12 ,  H01L29/458 ,  H01L29/4908

摘要： A thin film transistor array substrate is provided. The substrate includes an insulating substrate, a first signal line formed on the insulating substrate, a first insulating layer formed on the first signal line, a second signal line formed on the first insulating layer while crossing over the first signal line, a thin film transistor connected to the first and the second signal lines, a second insulating layer formed on the thin film transistor, the second insulating layer having dielectric constant about 4.0 or less, and the second insulating layer having a first contact hole exposing a predetermined electrode of the thin film transistor, and a first pixel electrode formed on the second insulating layer while being connected to the predetermined electrode of the thin film transistor through the first contact hole.

公开(公告)号：US20080145980A1

公开(公告)日：2008-06-19

申请号：US12030992

申请日：2008-02-14

申请人： Bo Sung KIM ,  Kwan-Wook JUNG ,  Wan-Shick HONG ,  Sang-Gab KIM ,  Mun-Pyo HONG

发明人： Bo Sung KIM ,  Kwan-Wook JUNG ,  Wan-Shick HONG ,  Sang-Gab KIM ,  Mun-Pyo HONG

IPC分类号： H01L21/336 ,  H01L21/4763

CPC分类号： G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1288

摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mas, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the firs wire via the contact holes.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔 使用感光膜作为蚀刻的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界，并且形成通过接触孔连接到第一线的第二线。

公开(公告)号：US20080121890A1

公开(公告)日：2008-05-29

申请号：US11950476

申请日：2007-12-05

申请人： Sung-Hoon YANG ,  Wan-Shick Hong ,  Kwan-Wook Jung

发明人： Sung-Hoon YANG ,  Wan-Shick Hong ,  Kwan-Wook Jung

IPC分类号： H01L29/786

CPC分类号： G02F1/136227 ,  C23C16/30 ,  G02F2001/136222 ,  H01L27/12 ,  H01L27/1248 ,  H01L27/1288 ,  H01L27/3244 ,  H01L29/458 ,  H01L29/4908 ,  H01L51/56

摘要： The present invention relates to a process for vapor depositing a low dielectric insulating film, a thin film transistor using the same, and a preparation method thereof, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device. The present invention also relates to a thin film transistor using the process and preparation method thereof.

摘要翻译： 本发明涉及一种用于气相沉积低介电绝缘膜的方法，使用其的薄膜晶体管及其制备方法，更具体地涉及可以显着改善蒸气的低介电绝缘膜的气相沉积方法 同时保持低介电绝缘膜的性能，从而解决了寄生电容问题，以实现高开口率结构，并且通过使用硅烷气体通过CVD或PECVD方法蒸镀绝缘膜时可以减少处理时间，以形成 用于半导体器件的保护膜。 本发明还涉及使用该方法及其制备方法的薄膜晶体管。

公开(公告)号：US06674495B1

公开(公告)日：2004-01-06

申请号：US09676813

申请日：2000-10-02

申请人： Mun-Pyo Hong ,  Wan-Shick Hong ,  Sang-Il Kim ,  Soo-Guy Rho ,  Jin-Kyu Kang ,  Snag-Gab Kim

发明人： Mun-Pyo Hong ,  Wan-Shick Hong ,  Sang-Il Kim ,  Soo-Guy Rho ,  Jin-Kyu Kang ,  Snag-Gab Kim

IPC分类号： G02F11336

CPC分类号： G02F1/136227 ,  G02F1/136209 ,  G02F1/136286 ,  G02F2001/136222 ,  H01L27/12 ,  H01L27/1255 ,  H01L27/1288 ,  H01L29/42384 ,  H01L29/4908

摘要： A black matrix having an opening at pixels of a matrix array in a display area, a common wire including common pads and common signal lines, and gate pads in a peripheral area, and an alignment key in outer area to align interlayer thin films are formed on an insulating substrate. Red, blue and green color filters the edge of which overlap the black matrix are formed at the pixels on the insulating substrate, and an organic insulating layer covering the black matrix and the color filters and having a contact hole exposing the gate pad is formed thereon. A gate wire including a gate line connected to the gate pad through the contact hole and a gate electrode connected to the gate line is formed on the organic insulating layer, and a gate insulating layer covering the gate wire is formed on the organic insulating layer. A semiconductor pattern and ohmic contact layers are sequentially formed on the gate insulating layer of the gate electrode. A data wire including a source electrode and a drain electrode that are made of a same layer on the ohmic contact layers and separated from each other, and a data line connected to the source electrode and defining the pixels of a matrix array by crossing the gate line is formed on the gate insulating layer. A passivation layer covering the data wire and having contact holes exposing the gate pad and the data pad is formed, and a pixel wire including a pixel electrode, a redundant gate pad, a redundant data pad that are respectively connected to the drain electrode, the gate pad and the data pad through the contact holes.

摘要翻译： 形成在显示区域中具有矩阵阵列的像素的开口的黑矩阵，包括公共焊盘和公共信号线的公共线，以及外围区域中的栅极焊盘以及外部区域中的对准键来对准层间薄膜 在绝缘基板上。 在绝缘基板上的像素处形成与黑矩阵重叠的边缘的红色，蓝色和绿色滤色片，并且在其上形成覆盖黑矩阵和滤色器并且具有暴露栅极接触孔的接触孔的有机绝缘层 。 在有机绝缘层上形成包括通过接触孔连接到栅极焊盘的栅极线和连接到栅极线的栅极的栅极线，并且在有机绝缘层上形成覆盖栅极线的栅极绝缘层。 半导体图案和欧姆接触层依次形成在栅电极的栅极绝缘层上。 一种数据线，包括在欧姆接触层上由相同层制成并彼此分离的源电极和漏电极，以及连接到源电极并通过跨越栅极定义矩阵阵列的像素的数据线 线形成在栅极绝缘层上。 形成覆盖数据线并具有露出栅极焊盘和数据焊盘的接触孔的钝化层，并且包括分别连接到漏电极的像素电极，冗余栅极焊盘，冗余数据焊盘的像素线， 栅极焊盘和数据焊盘通过接触孔。