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190 条记录 (耗时 0.03 秒)

    Thin film transistor and manufacturing method thereof
    1.
    发明授权
    Thin film transistor and manufacturing method thereof 有权
    薄膜晶体管及其制造方法

    公开(公告)号：US08871577B2

    公开(公告)日：2014-10-28

    申请号：US13436689

    申请日：2012-03-30

    申请人： Yeon Taek Jeong ,  Bo Sung Kim ,  Doo-Hyoung Lee ,  June Whan Choi ,  Tae-Young Choi ,  Kano Masataka

    发明人： Yeon Taek Jeong ,  Bo Sung Kim ,  Doo-Hyoung Lee ,  June Whan Choi ,  Tae-Young Choi ,  Kano Masataka

    IPC分类号： H01L21/00 ,  H01L29/423 ,  H01L29/49

    CPC分类号： H01L29/42384 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/512 ,  H01L29/786 ,  H01L2029/42388

    摘要： A thin film transistor is provided. A thin film transistor according to an exemplary embodiment of the present invention includes: a substrate; a gate line disposed on the substrate and including a gate electrode; a semiconductor layer disposed on the substrate and including at least a portion overlapping the gate electrode; a gate insulating layer disposed between the gate line and the semiconductor layer; and a source electrode and a drain electrode disposed on the substrate and facing each other over a channel region of the semiconductor layer. The gate insulating layer includes a first region and a second region, the first region corresponds to the channel region of the semiconductor layer, the first region is made of a first material, the second region is made of a second material, and the first material and the second material have different atomic number ratios of carbon and silicon.

    摘要翻译： 提供薄膜晶体管。 根据本发明的示例性实施例的薄膜晶体管包括：基板; 栅极线，设置在所述基板上并且包括栅电极; 半导体层，设置在所述基板上，并且至少包括与所述栅电极重叠的部分; 设置在所述栅极线和所述半导体层之间的栅极绝缘层; 以及设置在所述基板上并且在所述半导体层的沟道区域上彼此面对的源电极和漏电极。 栅极绝缘层包括第一区域和第二区域，第一区域对应于半导体层的沟道区域，第一区域由第一材料制成，第二区域由第二材料制成，第一材料 并且第二材料具有不同的碳和硅原子数比。

    METHOD AND APPARATUS FOR MANAGING AN APPLICATION BEING EXECUTED IN A PORTABLE TERMINAL
    4.
    发明申请
    METHOD AND APPARATUS FOR MANAGING AN APPLICATION BEING EXECUTED IN A PORTABLE TERMINAL 有权
    用于管理便携式终端中执行的应用程序的方法和装置

    公开(公告)号：US20110296418A1

    公开(公告)日：2011-12-01

    申请号：US13115881

    申请日：2011-05-25

    申请人： Bo-Sung KIM ,  Jong-Kyun SHIN ,  Hee-Deog KIM ,  Hyung-Chul JUNG

    发明人： Bo-Sung KIM ,  Jong-Kyun SHIN ,  Hee-Deog KIM ,  Hyung-Chul JUNG

    IPC分类号： G06F9/46

    CPC分类号： G06F3/04842 ,  G06F3/04817 ,  G06F11/328 ,  G06F11/3409 ,  Y02D10/34

    摘要： A method and an apparatus are provided for preventing battery power consumption and degradation of system performance due to the system resources being utilized by applications being executed, while providing a multi-tasking function through a plurality of applications. In the method, when a plurality of applications are executed, such execution of the plurality of applications is reported to the user, so as to enable the user to terminate one or more applications, thereby preventing unnecessary consumption of battery power.

    摘要翻译： 提供了一种方法和装置，用于防止电池电力消耗和系统性能的恶化，这是由于正被执行的应用程序正在利用的系统资源，同时通过多个应用提供多任务功能。 在该方法中，当执行多个应用时，向用户报告多个应用的​​执行，以使用户能够终止一个或多个应用，从而防止不必要的电池电力消耗。

    Thin film transistor array panel and manufacture thereof
    7.
    发明授权
    Thin film transistor array panel and manufacture thereof 有权
    薄膜晶体管阵列及其制造

    公开(公告)号：US07977144B2

    公开(公告)日：2011-07-12

    申请号：US12772845

    申请日：2010-05-03

    申请人： Seung-Hwan Cho ,  Bo-Sung Kim ,  Keun-Kyu Song ,  Tae-Young Choi ,  Jung-Hun Noh

    发明人： Seung-Hwan Cho ,  Bo-Sung Kim ,  Keun-Kyu Song ,  Tae-Young Choi ,  Jung-Hun Noh

    IPC分类号： H01L21/00

    CPC分类号： H01L51/0545 ,  H01L27/283 ,  H01L27/3244 ,  H01L51/0021

    摘要： A method for a thin film transistor array panel includes forming a gate line and a pixel electrode on a substrate, forming a gate insulating layer covering the gate line, forming a data line including a source electrode and a drain electrode on the gate insulating layer, forming an interlayer insulating layer covering the data line and the drain electrode on the gate insulating layer, forming a first opening in the interlayer insulating layer, forming an organic semiconductor in the first opening, forming a passivation layer on the organic semiconductor and the interlayer insulating layer, and forming a second opening in the interlayer insulating layer to expose the pixel electrode.

    摘要翻译： 一种薄膜晶体管阵列面板的制造方法，在基板上形成栅极线和像素电极，形成覆盖栅极线的栅极绝缘层，在栅极绝缘层上形成包括源电极和漏极的数据线， 在所述栅绝缘层上形成覆盖所述数据线和所述漏电极的层间绝缘层，在所述层间绝缘层中形成第一开口，在所述第一开口中形成有机半导体，在所述有机半导体上形成钝化层， 并且在所述层间绝缘层中形成第二开口以使所述像素电极露出。