公开(公告)号：US20070046435A1

公开(公告)日：2007-03-01

申请号：US11214262

申请日：2005-08-29

Applicant: Roger Fratti ,  Warren Waskiewicz

Inventor： Roger Fratti ,  Warren Waskiewicz

IPC: H04Q5/22

CPC classification number: G06K7/0008 ,  G06K7/10019

Abstract: RFID tags include circuitry operable to receive an input signal from a common transceiver and generate at least first and second signals, a first signal adapted to transmit information to the common transceiver and a second signal adapted to transmit information to adjacent RFID tags. The second adapted signal is received by the adjacent RFID tags and used to control their operation wherein they are temporarily disabled. During the time that the adjacent RFID tags are disabled, the first RFID tag communicates with the common transceiver via the first signal. When communication is complete the first RFID tags temporarily disable themselves allowing the adjacent RFID tags to be enabled and communicate with the common transceiver. In this manner only limited numbers of RFID tags are transmitting at one time thereby limiting the amount of RF power impinging upon the common transceiver. Spreading the RF power received by the common transceiver over time reduces the probability that the common transceiver will be overloaded or saturated improving the data transmission between RFID tags and common transceiver.

Abstract translation: RFID标签包括可操作以从公共收发器接收输入信号并产生至少第一和第二信号的电路，适于向公共收发器发送信息的第一信号和适于向相邻RFID标签发送信息的第二信号。 第二适配信号由相邻RFID标签接收并用于控制它们的操作，其中它们被暂时禁用。 在相邻RFID标签被禁用的时间内，第一RFID标签经由第一信号与公共收发器通信。 当通信完成时，第一RFID标签临时禁用自身，允许相邻RFID标签被启用并与公共收发器通信。 以这种方式，只有有限数量的RFID标签一次发送，从而限制了冲击在公共收发器上的RF功率的量。 普通收发器随时间传播RF功率可以降低普通收发器过载或饱和的可能性，从而改善RFID标签与公共收发器之间的数据传输。

公开(公告)号：US20050046326A1

公开(公告)日：2005-03-03

申请号：US10963156

申请日：2004-10-12

Applicant: Sungho Jin ,  Victor Katsap ,  Warren Waskiewicz ,  Wei Zhu

Inventor： Sungho Jin ,  Victor Katsap ,  Warren Waskiewicz ,  Wei Zhu

IPC: G03F7/20 ,  H01J1/15 ,  H01J1/18 ,  H01J9/02 ,  H01J9/04 ,  H01J37/06 ,  H01L21/027 ,  H01J1/14

CPC classification number: H01J1/15 ,  H01J9/042 ,  H01J37/06 ,  H01J2237/3175

Abstract: A cathode with an improved work function, for use in a lithographic system, such as the SCALPEL™ system, which includes a buffer between a substrate and an emissive layer, where the buffer alters, randomizes, miniaturizes, and/or isolates the grain structure at a surface of the substrate to reduce the grain size, randomize crystal orientation and reduce the rate of crystal growth. The buffer layer may be a solid solution or a multiphase alloy. A method of making the cathode by depositing a buffer between a surface of the substrate and an emissive layer, where the deposited buffer alters, randomizes, miniaturizes, and/or isolates the grain structure at a surface of the substrate to reduce the grain size, randomize crystal orientation and reduce the rate of crystal growth.

Abstract translation: 具有改进的功函数的阴极，用于诸如SCALPEL TM系统的光刻系统，其包括衬底和发射层之间的缓冲器，其中缓冲区改变，随机化，小型化和/或隔离 晶粒表面的晶粒结构减小晶粒尺寸，随机化晶体取向并降低晶体生长速率。 缓冲层可以是固溶体或多相合金。 通过在衬底的表面和发射层之间沉积缓冲剂来制造阴极的方法，其中沉积的缓冲液改变，随机化，小型化和/或隔离衬底表面处的晶粒结构以减小晶粒尺寸， 随机化晶体取向并降低晶体生长速率。

公开(公告)号：US20050026332A1

公开(公告)日：2005-02-03

申请号：US10628941

申请日：2003-07-29

Applicant: Roger Fratti ,  Warren Waskiewicz

Inventor： Roger Fratti ,  Warren Waskiewicz

IPC: H01L21/306 ,  H01L21/331 ,  H01L21/332 ,  H01L23/31 ,  H01L29/06 ,  H01L21/336

CPC classification number: H01L29/66234 ,  H01L21/30625 ,  H01L23/3171 ,  H01L29/66363 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Techniques for processing power transistor devices are provided. In one aspect, the curvature of a power transistor device comprising a device film formed on a substrate is controlled by thinning the substrate, the device having an overall residual stress attributable at least in part to the thinning step, and applying a stress compensation layer to a surface of the device film, the stress compensation layer having a tensile stress sufficient to counterbalance at least a portion of the overall residual stress of the device. The resultant power transistor device may be part of an integrated circuit.

Abstract translation: 提供了用于处理功率晶体管器件的技术。 在一个方面，包括形成在基板上的器件膜的功率晶体管器件的曲率通过使衬底变薄来控制，该器件具有至少部分归因于薄化步骤的总残余应力，并且将应力补偿层施加到 所述器件膜的表面，所述应力补偿层具有足以抵消所述器件的总残余应力的至少一部分的拉伸应力。 所得的功率晶体管器件可以是集成电路的一部分。