公开(公告)号：US6156601A

公开(公告)日：2000-12-05

申请号：US333961

申请日：1999-06-16

申请人： Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

发明人： Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

IPC分类号： G11C11/34 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10844 ,  H01L27/10805

摘要： A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.

摘要翻译： 动态随机存取存储器（DRAM）被组织为具有电容器对的基本组织单元的矩阵。 每个电容器对具有第一电容器和其中的第二电容器之一。 每个基本组织单元布置如下：在基板上形成作为平行线的第一字线和第二字线; 第一字线位于第一掺杂区和第二掺杂区之间，以限定第一晶体管; 第二字线位于第一晶体管的第二掺杂区域和第三掺杂区域之间，以限定第二晶体管; 位线以与第一字线和第二字线成倾斜的角度位于衬底的第二掺杂区域上; 第一电容器覆盖第一掺杂区域和第一字线，基本上位于第一掺杂区域的中心，经由第一接触孔连接到第一掺杂区域，并且具有六边形平面部分; 覆盖第三掺杂区域和第二字线的第二电容器基本上位于第三掺杂区域的中心，经由第二接触孔连接到第三掺杂区域，并且具有六边形平面部分; 并且基本组织单元的第一掺杂区域，第二掺杂区域和第三掺杂区域中的每一个的中心点可通过假想直线特征线连接。

公开(公告)号：US06246087B1

公开(公告)日：2001-06-12

申请号：US09217988

申请日：1998-12-22

申请人： Chang-Jae Lee ,  Won-Suck Yang

发明人： Chang-Jae Lee ,  Won-Suck Yang

IPC分类号： H01L27108

CPC分类号： H01L27/10852

摘要： A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

摘要翻译： 一种用于半导体存储器件的存储单元结构及其制造方法，其适用于需要非常高集成度的256M或更大容量的DRAM存储器件，其包括以下步骤：在半导体衬底上形成顺序的第一和第二随机层 ; 在第二随机层上图案化具有有限线宽度的第一光致抗蚀剂层; 使用图案化的第一光致抗蚀剂层作为掩模来图案化第二随机层; 去除第一光致抗蚀剂层，然后在第二无规层的图案之间图案化具有有限线宽度的第二光致抗蚀剂层; 使用如此构图的第二光致抗蚀剂层作为掩模来图案化第一无规层，以便放置在第二随机层的图案之间; 以及去除所述第二无规层和所述第二光致抗蚀剂层。

公开(公告)号：US5959321A

公开(公告)日：1999-09-28

申请号：US901876

申请日：1997-07-29

申请人： Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

发明人： Chang Jae Lee ,  Won Suck Yang ,  Kong Hee Park

IPC分类号： G11C11/34 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10844 ,  H01L27/10805

摘要： A dynamic random access memory (DRAM) organized as a matrix of basic organizational units each having a capacitor pair. Each capacitor pair has one of the first capacitors and one of the second capacitors in it. Each basic organizational unit is arranged as follows: a first word line and a second word line are formed, as parallel lines, on the substrate; the first word line lies between a first doped region and a second doped region to define a first transistor; the second word line lies between the second doped region of the first transistor and a third doped regions to define a second transistor; a bit line lies on the second doped region of the substrate at an oblique angle to the first word line and second word line; the first capacitor overlies the first doped region and the first word line, is substantially centered over the first doped region, is connected to the first doped region via a first contact hole, and has a hexagon-shaped planar portion; the second capacitor overlies the third doped region and the second word line, is substantially centered over the third doped region, is connected to the third doped region via a second contact hole, and has a hexagon-shaped planar portion; and a center point of each of the first doped region, second doped region and third doped region of the basic organizational unit are connectable by an imaginary straight characteristic line.

摘要翻译： 动态随机存取存储器（DRAM）被组织为具有电容器对的基本组织单元的矩阵。 每个电容器对具有第一电容器和其中的第二电容器之一。 每个基本组织单元布置如下：在基板上形成作为平行线的第一字线和第二字线; 第一字线位于第一掺杂区和第二掺杂区之间，以限定第一晶体管; 第二字线位于第一晶体管的第二掺杂区域和第三掺杂区域之间，以限定第二晶体管; 位线以与第一字线和第二字线成倾斜的角度位于衬底的第二掺杂区域上; 第一电容器覆盖第一掺杂区域和第一字线，基本上位于第一掺杂区域的中心，经由第一接触孔连接到第一掺杂区域，并且具有六边形平面部分; 覆盖第三掺杂区域和第二字线的第二电容器基本上位于第三掺杂区域的中心，经由第二接触孔连接到第三掺杂区域，并且具有六边形平面部分; 并且基本组织单元的第一掺杂区域，第二掺杂区域和第三掺杂区域中的每一个的中心点可通过假想直线特征线连接。

公开(公告)号：US5897350A

公开(公告)日：1999-04-27

申请号：US780173

申请日：1996-12-24

申请人： Chang-Jae Lee ,  Won-Suck Yang

发明人： Chang-Jae Lee ,  Won-Suck Yang

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10852

摘要： A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

摘要翻译： 一种用于半导体存储器件的存储单元结构及其制造方法，其适用于需要非常高集成度的256M或更大容量的DRAM存储器件，其包括以下步骤：在半导体衬底上形成顺序的第一和第二随机层 ; 在第二随机层上图案化具有有限线宽度的第一光致抗蚀剂层; 使用图案化的第一光致抗蚀剂层作为掩模来图案化第二随机层; 去除第一光致抗蚀剂层，然后在第二无规层的图案之间图案化具有有限线宽度的第二光致抗蚀剂层; 使用如此构图的第二光致抗蚀剂层作为掩模来构图第一随机层，以便放置在第二随机层的图案之间; 以及去除所述第二无规层和所述第二光致抗蚀剂层。