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    Data error control
    1.
    发明授权
    Data error control 有权
    数据错误控制

    公开(公告)号：US07716566B2

    公开(公告)日：2010-05-11

    申请号：US11187737

    申请日：2005-07-22

    Applicant: Xiaobing Lee ,  David J. Agans ,  Bruce E. Mann

    Inventor： Xiaobing Lee ,  David J. Agans ,  Bruce E. Mann

    IPC: H03M13/00

    CPC classification number: H04L1/0045 ,  G06F11/1092 ,  H03M13/11 ,  H03M13/373 ,  H03M13/3746 ,  H04L1/0041 ,  H04L1/0057 ,  H04L2001/0096

    Abstract: Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one item from one or more of the other parity fields. A decoder can regenerate as many as M missing or corrupted fields of either data or parity using combinations of correct and/or previously corrected items as inputs using M independent parity equations to solve for and correct each missing or corrupted item in turn.

    Abstract translation: 数据存储或数据通信系统中的多个损坏和/或擦除被更正。 编码器从N个数据信道生成奇偶校验字段的M个。 生成的奇偶校验字段的每个项目是对来自一个或多个数据字段的一个项目以及可能一个来自一个或多个其他奇偶校验字段的项目的简单的异或操作的结果。 解码器可以使用正确和/或先前校正的项目的组合作为使用M个独立奇偶校验方程的输入来再生多达M个丢失或损坏的数据或奇偶校验字段，以依次解决和纠正每个丢失或损坏的项目。

    Latency-based statistical multiplexing
    2.
    发明授权
    Latency-based statistical multiplexing 失效
    基于延迟的统计复用

    公开(公告)号：US06665872B1

    公开(公告)日：2003-12-16

    申请号：US09478127

    申请日：2000-01-05

    Applicant: Ravi Krishnamurthy ,  Sriram Sethuraman ,  Xiaobing Lee ,  Tihao Chiang

    Inventor： Ravi Krishnamurthy ,  Sriram Sethuraman ,  Xiaobing Lee ,  Tihao Chiang

    IPC: H04J316

    CPC classification number: H04N21/2365 ,  H04N19/115 ,  H04N19/124 ,  H04N19/14 ,  H04N19/149 ,  H04N19/15 ,  H04N19/152 ,  H04N19/159 ,  H04N19/172 ,  H04N19/177 ,  H04N19/179 ,  H04N19/42 ,  H04N19/61 ,  H04N21/23655 ,  H04N21/238 ,  H04N21/4347

    Abstract: When two or more different video streams a e compressed for concurrent transmission of multiple compressed video bitstreams over a single shared communication channel, control over both (1) the transmission of data over the shared channel and (2) the compression processing that generates the bitstreams is exercised taking into account the differing levels of latency required for the corresponding video applications. For example, interactive video games typically require lower latency than other video applications such as video streaming, web browsing, and electronic mail. A multiplexer and traffic controller takes these differing latency requirements, along with bandwidth and image fidelity requirements, into account when controlling both traffic flow and compression processing. In addition, an off-line profiling tool analyzes typical video applications off-line in order to generate profiles of different types of video applications that are then accessed in real-time by a call admission manager responsible to controlling the admission of new video application sessions as well as the assignment of admitted applications to specific available video encoders, which themselves may differ in video compression processing power as well as in the degree to which they allow external processors (like the multiplexer and traffic controller) to control their internal compression processing.

    Abstract translation: 当两个或多个不同的视频流被压缩以通过单个共享通信信道同时传输多个压缩视频比特流时，可以对共享信道上的数据传输进行控制（2）产生比特流的压缩处理是 考虑到相应视频应用程序所需的等待时间不同的行为。 例如，交互式视频游戏通常比其他视频应用（例如视频流，网页浏览和电子邮件）需要更低的延迟。 多路复用器和流量控制器在控制流量和压缩处理两者时考虑到这些不同的延迟要求以及带宽和图像保真度要求。 此外，离线分析工具可以离线分析典型的视频应用程序，以便生成不同类型的视频应用程序的配置文件，然后由负责控制新视频应用程序会话的呼叫接纳管理员实时访问 以及将允许的应用分配给特定可用的视频编码器，它们本身可能在视频压缩处理能力方面可能不同，以及允许外部处理器（如多路复用器和流量控制器）控制其内部压缩处理的程度。

    Data error control
    3.
    发明授权
    Data error control 有权
    数据错误控制

    公开(公告)号：US07882425B2

    公开(公告)日：2011-02-01

    申请号：US12728832

    申请日：2010-03-22

    Applicant: Xiaobing Lee ,  David J. Agans ,  Bruce E. Mann

    Inventor： Xiaobing Lee ,  David J. Agans ,  Bruce E. Mann

    IPC: H03M13/00

    CPC classification number: H04L1/0045 ,  G06F11/1092 ,  H03M13/11 ,  H03M13/373 ,  H03M13/3746 ,  H04L1/0041 ,  H04L1/0057 ,  H04L2001/0096

    Abstract: Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one item from one or more of the other parity fields. A decoder can regenerate as many as M missing or corrupted fields of either data or parity using combinations of correct and/or previously corrected items as inputs using M independent parity equations to solve for and correct each missing or corrupted item in turn.

    Abstract translation: 数据存储或数据通信系统中的多个损坏和/或擦除被更正。 编码器从N个数据信道生成奇偶校验字段的M个。 生成的奇偶校验字段的每个项目是对来自一个或多个数据字段的一个项目以及可能一个来自一个或多个其他奇偶校验字段的项目的简单的异或操作的结果。 解码器可以使用正确和/或先前校正的项目的组合作为使用M个独立奇偶校验方程的输入来再生多达M个丢失或损坏的数据或奇偶校验字段，以依次解决和纠正每个丢失或损坏的项目。

    Data error control
    5.
    发明申请
    Data error control 有权
    数据错误控制

    公开(公告)号：US20060156178A1

    公开(公告)日：2006-07-13

    申请号：US11187737

    申请日：2005-07-22

    Applicant: Xiaobing Lee ,  David Agans ,  Bruce Mann

    Inventor： Xiaobing Lee ,  David Agans ,  Bruce Mann

    IPC: H03M13/00

    CPC classification number: H04L1/0045 ,  G06F11/1092 ,  H03M13/11 ,  H03M13/373 ,  H03M13/3746 ,  H04L1/0041 ,  H04L1/0057 ,  H04L2001/0096

    Abstract: Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one item from one or more of the other parity fields. A decoder can regenerate as many as M missing or corrupted fields of either data or parity using combinations of correct and/or previously corrected items as inputs using M independent parity equations to solve for and correct each missing or corrupted item in turn.

    Abstract translation: 数据存储或数据通信系统中的多个损坏和/或擦除被更正。 编码器从N个数据信道生成奇偶校验字段的M个。 生成的奇偶校验字段的每个项目是对来自一个或多个数据字段的一个项目以及可能一个来自一个或多个其他奇偶校验字段的项目的简单的异或操作的结果。 解码器可以使用正确和/或先前校正的项目的组合作为使用M个独立奇偶校验方程的输入来再生多达M个丢失或损坏的数据或奇偶校验字段，以依次解决和纠正每个丢失或损坏的项目。

    Computer system for statistical multiplexing of bitstreams
    6.
    发明授权
    Computer system for statistical multiplexing of bitstreams 有权
    用于比特流统计复用的计算机系统

    公开(公告)号：US06754241B1

    公开(公告)日：2004-06-22

    申请号：US09478128

    申请日：2000-01-05

    Applicant: Ravi Krishnamurthy ,  Sriram Sethuraman ,  Xiaobing Lee ,  Tihao Chiang

    Inventor： Ravi Krishnamurthy ,  Sriram Sethuraman ,  Xiaobing Lee ,  Tihao Chiang

    IPC: H04J302

    CPC classification number: H04N21/23655 ,  H04N19/115 ,  H04N19/14 ,  H04N19/15 ,  H04N19/152 ,  H04N19/159 ,  H04N19/172 ,  H04N19/177 ,  H04N19/179 ,  H04N19/42 ,  H04N19/61 ,  H04N21/2365 ,  H04N21/238 ,  H04N21/4347

    Abstract: A PC-type computer has a system bus (e.g., a PCI bus) configured with a main CPU board, a statistical multiplexing (stat-mux) board, and a plurality of video/audio encoder boards, each configured to receive and compress a corresponding video/audio stream. The stat-mux board performs statistical multiplexing on the different compressed bitstreams to transmit multiple bitstreams over individual shared communication channels. Although each of the boards is configured to the system bus, each encoder board has a digital signal processor (DSP) with a synchronized serial interface (SSI) output port that is directly connected to an SSI input port on a DSP on the stat-mux board (which, in one embodiment, has four such DSPs each with six such SSI input ports). As such, (up to 24) compressed video/audio bitstreams generated on the various encoder boards can be transmitted directly to the stat-mux board without having to go through the system bus. In this way, the computer system can provide statistical multiplexing of low-latency video/audio bitstreams without having to suffer the processing delays associated with conventional transmission over PCI system buses.

    Abstract translation: PC型计算机具有配置有主CPU板，统计复用（stat-mux）板和多个视频/音频编码器板的系统总线（例如，PCI总线），每个配置用于接收和压缩 相应的视频/音频流。 统计复用板对不同的压缩比特流执行统计复用，以在各个共享通信信道上传输多个比特流。 虽然每个板都配置为系统总线，但每个编码器板都有一个数字信号处理器（DSP），具有同步的串行接口（SSI）输出端口，它直接连接到数模转换器上的DSP上的SSI输入端口 板（在一个实施例中，具有四个这样的DSP，每个具有六个这样的SSI输入端口）。 因此，在各种编码器板上生成的（多达24个）压缩视频/音频比特流可以直接发送到统一复用板，而不必通过系统总线。 以这种方式，计算机系统可以提供低延迟视频/音频比特流的统计复用，而不必忍受与PCI系统总线上的常规传输相关联的处理延迟。

    Data Error Control
    7.
    发明申请
    Data Error Control 有权
    数据错误控制

    公开(公告)号：US20100192049A1

    公开(公告)日：2010-07-29

    申请号：US12728832

    申请日：2010-03-22

    Applicant: Xiaobing Lee ,  David J. Agans ,  Bruce E. Mann

    Inventor： Xiaobing Lee ,  David J. Agans ,  Bruce E. Mann

    IPC: H03M13/11 ,  G06F11/10

    CPC classification number: H04L1/0045 ,  G06F11/1092 ,  H03M13/11 ,  H03M13/373 ,  H03M13/3746 ,  H04L1/0041 ,  H04L1/0057 ,  H04L2001/0096

    Abstract: Multiple corruptions and/or erasures in data storage or data communication systems are corrected. An encoder generates M of parity fields from N data channels. Each item of the generated parity fields is the result of simple exclusive-or operations on one item from one or more data fields and possibly one item from one or more of the other parity fields. A decoder can regenerate as many as M missing or corrupted fields of either data or parity using combinations of correct and/or previously corrected items as inputs using M independent parity equations to solve for and correct each missing or corrupted item in turn.

    Abstract translation: 数据存储或数据通信系统中的多个损坏和/或擦除被更正。 编码器从N个数据信道生成奇偶校验字段的M个。 生成的奇偶校验字段的每个项目是对来自一个或多个数据字段的一个项目以及可能一个来自一个或多个其他奇偶校验字段的项目的简单的异或操作的结果。 解码器可以使用正确和/或先前校正的项目的组合作为使用M个独立奇偶校验方程的输入来再生多达M个丢失或损坏的数据或奇偶校验字段，以依次解决和纠正每个丢失或损坏的项目。

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