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1.发明授权Static random access memory cell with single-sided buffer and asymmetric construction 有权静态随机存取存储单元采用单面缓冲和非对称构造公开(公告)号：US08654562B2
公开(公告)日：2014-02-18
申请号：US13477901
申请日：2012-05-22
申请人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Zhonghai Shi
发明人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Zhonghai Shi
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C11/412 , H01L27/1104
摘要： Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.
摘要翻译： 在具有不对称上下文（例如缓冲电路）的静态随机存取存储器（SRAM）单元中的平衡电性能。 每个存储单元包括诸如读缓冲器的电路特征，其具有比单元内的其它晶体管更大的晶体管尺寸和特征，并且其中特征不对称影响较小单元晶体管。 为了获得最佳性能，单元晶体管对将彼此电气匹配。 更接近不对称特征的单元晶体管中的一个或多个不同地构成，例如具有不同的沟道宽度，沟道长度或净沟道掺杂剂浓度，以补偿不对称特征的邻近效应。
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2.发明申请Static Random Access Memory Cell with Single-Sided Buffer and Asymmetric Construction 有权具有单边缓冲和静态随机存取存储单元的非对称结构公开(公告)号：US20130182490A1
公开(公告)日：2013-07-18
申请号：US13477901
申请日：2012-05-22
申请人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Zhonghai Shi
发明人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Zhonghai Shi
CPC分类号： G11C11/413 , G11C11/412 , H01L27/1104
摘要： Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.
摘要翻译： 在具有不对称上下文（例如缓冲电路）的静态随机存取存储器（SRAM）单元中的平衡电性能。 每个存储单元包括诸如读缓冲器的电路特征，其具有比单元内的其它晶体管更大的晶体管尺寸和特征，并且其中特征不对称影响较小单元晶体管。 为了获得最佳性能，单元晶体管对将彼此电气匹配。 更接近不对称特征的单元晶体管中的一个或多个不同地构成，例如具有不同的沟道宽度，沟道长度或净沟道掺杂剂浓度，以补偿不对称特征的邻近效应。
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公开(公告)号：US20120106225A1
公开(公告)日：2012-05-03
申请号：US12913479
申请日：2010-10-27
申请人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Terence G. W. Blake
发明人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Terence G. W. Blake
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , G11C5/025 , Y02P90/265
摘要： An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.
摘要翻译： 一种用于生成集成电路的布局的集成电路和方法，其中根据类似于单元本身构造的器件在一个或多个结构级别中实现诸如存储器或逻辑单元的重复特征阵列的外围电路。 确定在各种水平上引起邻近效应的距离。 这些接近效应距离决定了在每个级别的阵列之外和之后重复的那些特征的数量，其中构造外围电路以匹配阵列中的重复特征的构造。
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公开(公告)号：US08472228B2
公开(公告)日：2013-06-25
申请号：US12913479
申请日：2010-10-27
申请人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Terence G. W. Blake
发明人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Terence G. W. Blake
CPC分类号： G06F17/5068 , G06F17/5081 , G06F2217/12 , G11C5/025 , Y02P90/265
摘要： An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or more structural levels. The distance over which proximity effects are caused in various levels is determined. Those proximity effect distances determine the number of those features to be repeated outside of and adjacent to the array for each level, within which the peripheral circuitry is constructed to match the construction of the repetitive features in the array.
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5.发明授权Method of screening static random access memory cells for positive bias temperature instability 有权静态随机存取存储单元筛选正偏温度不稳定性的方法公开(公告)号：US08971138B2
公开(公告)日：2015-03-03
申请号：US13467517
申请日：2012-05-09
申请人： Anand Seshadri , Wah Kit Loh
发明人： Anand Seshadri , Wah Kit Loh
CPC分类号： G11C29/50 , G11C11/41 , G11C29/06 , G11C29/50004 , G11C29/50016 , G11C2029/5002
摘要： A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.
摘要翻译： 一种互补金属氧化物半导体CMOS集成电路的方法，例如包括CMOS静态随机存取存储器（SRAM）单元的集成电路，用于易于经过工作时间的晶体管特性偏移的n沟道晶体管。 对于由交叉耦合CMOS反相器形成的SRAM单元的示例，提供静态噪声容限和可写性（Vtrip）屏幕。 CMOS SRAM单元中的每个n沟道晶体管形成在与存储器的外围电路中的p型半导体材料和集成电路中的其它功能隔离的p阱内。 正向和反向体节点偏置电压被施加到待测SRAM单元的隔离p阱，以确定读取干扰或写周期这样的操作是否会在这种偏差下破坏单元。 因此可以识别易受阈值电压偏移的电池。
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6.发明申请Method of Screening Static Random Access Memory Cells for Positive Bias Temperature Instability 有权筛选静态随机存取存储器单元的正偏差温度不稳定性的方法公开(公告)号：US20130058177A1
公开(公告)日：2013-03-07
申请号：US13467517
申请日：2012-05-09
申请人： Anand Seshadri , Wah Kit Loh
发明人： Anand Seshadri , Wah Kit Loh
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/41 , G11C29/06 , G11C29/50004 , G11C29/50016 , G11C2029/5002
摘要： A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.
摘要翻译： 一种互补金属氧化物半导体CMOS集成电路的方法，例如包括CMOS静态随机存取存储器（SRAM）单元的集成电路，用于易于经过工作时间的晶体管特性偏移的n沟道晶体管。 对于由交叉耦合CMOS反相器形成的SRAM单元的示例，提供静态噪声容限和可写性（Vtrip）屏幕。 CMOS SRAM单元中的每个n沟道晶体管形成在与存储器的外围电路中的p型半导体材料和集成电路中的其它功能隔离的p阱内。 正向和反向体节点偏置电压被施加到待测SRAM单元的隔离p阱，以确定读取干扰或写周期这样的操作是否会在这种偏差下破坏单元。 因此可以识别易受阈值电压偏移的电池。
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7.发明授权公开(公告)号：US08560931B2
公开(公告)日：2013-10-15
申请号：US13483897
申请日：2012-05-30
申请人： Anand Seshadri , Wah Kit Loh
发明人： Anand Seshadri , Wah Kit Loh
CPC分类号： G06F11/1048 , G11C11/41 , G11C29/42 , G11C29/50016 , H03M13/13 , H03M13/19
摘要： Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.
摘要翻译： 固态随机存取存储器包括应用于进入和退出数据保留模式的存储器阵列的纠错能力。 在确定存储器的一部分要进入数据保持模式时执行要保留的数据的纠错编码; 奇偶校验位（即除了存储有效载荷所需的位之外的位）存储在保留域内或外部的可用存储单元中。 退出保留模式后，对代码字进行解码以纠正任何错误，并将有效载荷数据返回到原始单元格。 在正常工作模式下不进行纠错编码和解码。
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8.发明申请Low Power Retention Random Access Memory with Error Correction on Wake-Up 有权低功耗保持随机存取存储器，具有唤醒时的纠错功能公开(公告)号：US20120324314A1
公开(公告)日：2012-12-20
申请号：US13483897
申请日：2012-05-30
申请人： Anand Seshadri , Wah Kit Loh
发明人： Anand Seshadri , Wah Kit Loh
CPC分类号： G06F11/1048 , G11C11/41 , G11C29/42 , G11C29/50016 , H03M13/13 , H03M13/19
摘要： Solid-state random access memory including error correction capability applied to memory arrays entering and exiting a data retention mode. Error correction coding of the data to be retained is performed upon determining that a portion of the memory is to enter data retention mode; the parity bits (i.e., bits in addition to those required for storage of the payload) are stored in available memory cells within or external to the retention domain. Upon exit from retention mode, the code words are decoded to correct any errors, and the payload data are returned to the original cells. Error correction encoding and decoding is not performed in the normal operating mode.
摘要翻译： 固态随机存取存储器包括应用于进入和退出数据保留模式的存储器阵列的纠错能力。 在确定存储器的一部分要进入数据保持模式时执行要保留的数据的纠错编码; 奇偶校验位（即除了存储有效载荷所需的位之外的位）存储在保留域内或外部的可用存储单元中。 退出保留模式后，对代码字进行解码以纠正任何错误，并将有效载荷数据返回到原始单元格。 在正常工作模式下不进行纠错编码和解码。
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公开(公告)号：US08339839B2
公开(公告)日：2012-12-25
申请号：US13363051
申请日：2012-01-31
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage.
摘要翻译： 包含单面写入SRAM单元阵列的第一集成电路，每个SRAM单元具有位通道和辅助位棒驱动晶体管。 包括单向读取操作的第一集成电路的处理，其中寻址单元和半寻址单元中的辅助驱动器的源节点浮动。 包含SRAM单元阵列的第二集成电路，其中每个SRAM单元包括位侧写入通道，位线侧读取通道和位线辅助驱动器晶体管。 包括单向读取操作的第二集成电路的处理，其中寻址单元和半寻址单元中的辅助驱动器的源节点被偏置到低偏置电压。
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10.发明授权Apparatus and method for accelerating simulations and designing integrated circuits and other systems 有权用于加速模拟和设计集成电路和其他系统的装置和方法公开(公告)号：US08301431B2
公开(公告)日：2012-10-30
申请号：US12346036
申请日：2008-12-30
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/10
摘要： A method of accelerating a Monte Carlo (MC) simulation for a system including a first component having a first input parameter and a second component having a second input parameter. The simulation model provided includes a first component model including a first model parameter corresponding to the first input parameter and a second component model having a second model parameter corresponding to the second input parameter. A first acceleration factor for the first component and a second acceleration factor for the second component are calculated based on at least the respective number of instances. A first scaled distribution is computed from the first distribution and a second scaled distribution is computed from the second distribution based on the respective acceleration factors. The MC simulation for the system is run, wherein values for the first model parameter value and second model parameter value are obtained based on the respective scaled distributions.
摘要翻译： 一种加速用于包括具有第一输入参数的第一分量和具有第二输入参数的第二分量的系统的系统的蒙特卡罗（MC）模拟的方法。 提供的模拟模型包括第一分量模型，其包括对应于第一输入参数的第一模型参数和具有对应于第二输入参数的第二模型参数的第二分量模型。 至少基于相应数量的实例来计算第一分量的第一加速因子和第二分量的第二加速因子。 从第一分布计算第一缩放分布，并且基于相应的加速因子从第二分布计算第二缩放分布。 运行系统的MC模拟，其中基于相应的缩放分布获得第一模型参数值和第二模型参数值的值。
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