公开(公告)号：US20170042380A1

公开(公告)日：2017-02-16

申请号：US15234335

申请日：2016-08-11

Applicant: Wei-Chih LIN ,  Ya-Chun CHANG ,  Chin-Jui LIEN ,  Lee Keong WONG

Inventor： Tzu-Nung LIN

IPC: A47J43/07 ,  A47J43/08

CPC classification number: A47J43/0716 ,  A47J19/02 ,  A47J43/085 ,  A47J43/087 ,  A47J44/00

Abstract: A juicer comprises a base. A motor electrically connected to a controller disposed inside the base. The controller controls an axis of the motor to turn clockwise or anti-clockwise. The axis of the motor has a first end and a second end in an opposite direction to the first end. The first end of the axis is axially connected with a first unidirectional bearing coupled with a first connecting element coaxially. The second end of the axis is axially connected with a second unidirectional bearing coupled with a second connecting element coaxially. The second connecting element is moved together with a third connecting element. Thereby, the axis of the motor turns in clockwise or anti-clockwise direction for selectively enabling the first connecting element to move upwardly together with a first cutter inside a first container and to turn the first cutter for cutting.

Abstract translation: 榨汁机包括一个基地。 电连接到设置在基座内的控制器的电动机。 控制器控制电机的轴顺时针或逆时针旋转。 马达的轴线具有与第一端相反的方向的第一端和第二端。 轴的第一端与同轴地与第一连接元件联接的第一单向轴承轴向连接。 轴的第二端与同轴地与第二连接元件联接的第二单向轴承轴向连接。 第二连接元件与第三连接元件一起移动。 因此，马达的轴线顺时针或逆时针方向转动，以便选择性地使第一连接元件与第一切割器在第一容器内部一起向上移动并转动第一切割器进行切割。

公开(公告)号：US20140032816A1

公开(公告)日：2014-01-30

申请号：US13559600

申请日：2012-07-27

Applicant: Yung-Chen Lin ,  Ya-Chun Chang

Inventor： Yung-Chen Lin ,  Ya-Chun Chang

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G06F12/1425 ,  G11C7/20

Abstract: A serial interface flash memory apparatus and a writing method for a status register thereof are disclosed. The writing method for the status register mentioned above includes: receiving a write command with an updated data for the status register; writing the updated data to a volatile latch and set an update flag according to whether or not a write-protected data in the status register is updated by the write command; and writing the data from the volatile latch to the status register according to the update flag when a power down process of the serial interface flash memory apparatus is processed.

Abstract translation: 公开了串行接口闪存装置及其状态寄存器的写入方法。 上述状态寄存器的写入方法包括：接收具有状态寄存器的更新数据的写命令; 将更新的数据写入易失性锁存器，并根据写命令来更新状态寄存器中的写保护数据是否设置更新标志; 以及当串行接口闪存设备的断电过程被处理时，根据更新标志将数据从易失性锁存器写入状态寄存器。

公开(公告)号：US07402411B2

公开(公告)日：2008-07-22

申请号：US11318907

申请日：2005-12-27

Applicant: Ya-Chun Chang ,  Yueh-Chwen Hsu ,  Tzu-Jung Yeh

Inventor： Ya-Chun Chang ,  Yueh-Chwen Hsu ,  Tzu-Jung Yeh

IPC: C12P19/34 ,  C12Q1/68 ,  C07H21/04

CPC classification number: C12Q1/701 ,  C12Q1/6895

Abstract: The inventions provides a method for identifying a target virus in an infected subject comprising the steps of designing a pair of degenerate primers corresponding to highly conserved regions of the target virus; designing a pair of species-specific primers according to highly variable sequences within the conserved regions of the target virus; preparing the species-specific probes according to the larger sequence variations within the conserved regions of the target virus, which are amplified with the species-specific primers as obtained; preparing a test sample by amplifying total nucleic acid of the infected subject with the degenerate primers as obtained; contacting the test sample with the species-specific probes as obtained; and detecting a hybridization between the species-specific probe and the test sample, wherein the hybridization indicates the target virus is identified in the infected subject. The primers and probes for detecting a garget virus are also provided.

Abstract translation: 本发明提供了一种用于鉴定感染对象中的靶病毒的方法，包括以下步骤：设计对应于目标病毒的高度保守区域的简并引物对; 根据目标病毒保守区域内高度可变序列设计一对物种特异性引物; 根据目标病毒保守区域内较大的序列变异制备物种特异性探针，其用获得的物种特异性引物扩增; 通过用所得的简并引物扩增感染受试者的总核酸来制备测试样品; 使测试样品与获得的物种特异性探针接触; 并检测物种特异性探针和测试样品之间的杂交，其中杂交表明在感染的受试者中鉴定出靶病毒。 还提供了用于检测靶标病毒的引物和探针。

公开(公告)号：US20080002511A1

公开(公告)日：2008-01-03

申请号：US11649816

申请日：2007-01-05

Applicant: Chi Yuan Mou ,  Chien Hao Lu ,  Wen Pin Hsieh ,  Ya Chun Chang

Inventor： Chi Yuan Mou ,  Chien Hao Lu ,  Wen Pin Hsieh ,  Ya Chun Chang

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: A semiconductor memory and address-decoding circuit and method for decoding address allow the semiconductor memory to operate under a decreased capacity by disabling or hiding a predetermined portion of the semiconductor memory. The semiconductor memory comprises a first address-inputting circuit configured to receive a first external address, a switching circuit configured to switch a predetermined portion of the first external address to form an internal address, at least one address-setting code configured to set at least one predetermined bit of the internal address, a decoder coupling to the switching circuit and the address-setting code, and a memory array coupling to the decoder, wherein the decoder is configured to select at least one memory unit of the memory array based on the internal address. The first address-inputting circuit, the switching circuit and the address-setting code can be considered as an address-decoding circuit.

Abstract translation: 用于解码地址的半导体存储器和地址解码电路和方法允许半导体存储器通过禁止或隐藏半导体存储器的预定部分而在降低的容量下工作。 所述半导体存储器包括被配置为接收第一外部地址的第一地址输入电路，被配置为切换所述第一外部地址的预定部分以形成内部地址的开关电路，至少一个地址设置码被配置为至少设置 内部地址的一个预定位，耦合到开关电路的解码器和地址设置代码，以及耦合到解码器的存储器阵列，其中解码器被配置为基于该解码器选择存储器阵列的至少一个存储器单元 内部地址 第一地址输入电路，开关电路和地址设定码可以被认为是地址解码电路。

公开(公告)号：US5862073A

公开(公告)日：1999-01-19

申请号：US931065

申请日：1997-09-15

Applicant: Jun-Lin Yeh ,  Ya-Chun Chang

Inventor： Jun-Lin Yeh ,  Ya-Chun Chang

IPC: G11C16/04 ,  G11C16/08 ,  G11C7/00

CPC classification number: G11C16/08 ,  G11C16/0416

Abstract: A semiconductor memory array and method for use in a memory device in which the location of a memory cell in the array is specified by row address and column address decoders. The memory cells may be floating gate memory cells in which data is programmed by hot carrier injection and erased by Fowler-Nordheim tunneling. The array includes bit lines connected to the column address decoder, and word lines and N+ diffusion source lines connected to the row address decoder. Each memory cell has a gate connected to a word line, a drain connected to a bit line and a source connected to the N+ diffusion source line. A low resistance source line formed of metal II or other conductive material is arranged adjacent to each N+ source line and is electrically connected thereto at one or more locations via interconnecting straps. The low resistance source lines serve to reduce the voltage drop across the N+ diffusion source lines during program operations and provide an improved ground connection during read operations. The word lines are grouped into pairs of even and odd word lines and each pair makes up the minimum program unit or page. The page is also the minimum erase unit, such that adjacent even and odd word lines are erased simultaneously. The voltage applied to a given word line during a read operation may be supplied by a word line clamping circuit which limits gate disturbances resulting from fluctuations in supply voltage.

Abstract translation: 一种在存储器件中使用的半导体存储器阵列和方法，其中阵列中的存储单元的位置由行地址和列地址解码器指定。 存储器单元可以是浮动栅极存储单元，其中通过热载流子注入来编程数据，并通过Fowler-Nordheim隧道擦除数据。 阵列包括连接到列地址解码器的位线，以及连接到行地址解码器的字线和N +扩散源线。 每个存储单元具有连接到字线的栅极，连接到位线的漏极和连接到N +扩散源线的源极。 由金属II或其他导电材料形成的低电阻源极线布置成与每个N +源极线相邻，并且通过互连带在一个或多个位置处电连接到其上。 低电阻源线用于在编程操作期间减小N +扩散源线上的电压降，并在读取操作期间提供改进的接地连接。 字线被分组成偶数和奇数字线对，每对组成最小程序单元或页面。 该页面也是最小擦除单元，使得相邻的偶数和奇数字线同时被擦除。 在读取操作期间施加到给定字线的电压可以由限制由电源电压波动引起的栅极干扰的字线钳位电路提供。

公开(公告)号：US08751730B2

公开(公告)日：2014-06-10

申请号：US13559600

申请日：2012-07-27

Applicant: Yung-Chen Lin ,  Ya-Chun Chang

Inventor： Yung-Chen Lin ,  Ya-Chun Chang

IPC: G06F12/02 ,  G06F11/10 ,  G11C7/20

CPC classification number: G06F12/0246 ,  G06F11/1068 ,  G06F12/1425 ,  G11C7/20

Abstract: A serial interface flash memory apparatus and a writing method for a status register thereof are disclosed. The writing method for the status register mentioned above includes: receiving a write command with an updated data for the status register; writing the updated data to a volatile latch and set an update flag according to whether or not a write-protected data in the status register is updated by the write command; and writing the data from the volatile latch to the status register according to the update flag when a power down process of the serial interface flash memory apparatus is processed.

Abstract translation: 公开了串行接口闪存装置及其状态寄存器的写入方法。 上述状态寄存器的写入方法包括：接收具有状态寄存器的更新数据的写命令; 将更新的数据写入易失性锁存器，并根据写命令来更新状态寄存器中的写保护数据是否设置更新标志; 以及当串行接口闪存设备的断电过程被处理时，根据更新标志将数据从易失性锁存器写入状态寄存器。

公开(公告)号：US20170035252A1

公开(公告)日：2017-02-09

申请号：US15230087

申请日：2016-08-05

Applicant: Wei-Chih LIN ,  Ya-Chun CHANG ,  Chin-Jui LIEN ,  Lee Keong WONG

Inventor： Tzu-Nung LIN

IPC: A47J43/07

CPC classification number: A47J43/0722 ,  A47J19/02 ,  A47J19/06 ,  A47J43/046 ,  A47J43/0716 ,  B26D7/0641

Abstract: A cover of a processor for fruits and vegetables is connected above a cutter. The cover comprises a cover body and a container. The cover body has a feed tube. The feed tube has an accommodating space running through vertically. A first positioning element is disposed on an outer circumference of the feed tube. The cover body having a water inlet hole through which the accommodating space is in communication with an outside of the cover body. A second positioning element correspondingly connected with the first positioning element disposed on a side of the container, so that the container and the feed tube are connected with each other. A water outlet end is disposed at a bottom of the container for correspondingly being communication with the water inlet hole; thereby, water in the container flows from the water outlet end into the accommodating space through the water inlet hole.

Abstract translation: 用于水果和蔬菜的处理器的盖子连接在切割器上方。 盖子包括盖体和容器。 盖体具有进料管。 进料管具有垂直延伸的容纳空间。 第一定位元件设置在进料管的外圆周上。 盖体具有进水孔，容纳空间通过该入口孔与盖体的外部连通。 第二定位元件与设置在容器侧的第一定位元件对应地连接，使得容器和进料管彼此连接。 水出口端设置在容器的底部，用于相应地与进水孔连通; 从而容器中的水通过进水孔从出水端流入容纳空间。

公开(公告)号：US20120158208A1

公开(公告)日：2012-06-21

申请号：US13313103

申请日：2011-12-07

Applicant: Tomohiro Kawamoto ,  Ya-chun Chang

Inventor： Tomohiro Kawamoto ,  Ya-chun Chang

IPC: G05D1/00

CPC classification number: B62K11/007 ,  B60L2200/16 ,  B60L2220/46 ,  B60L2240/18 ,  B60L2240/20 ,  B60L2240/26 ,  B60L2260/34

Abstract: An inverted pendulum type moving body. The inverted pendulum type moving body includes: a vehicle body having a riding part on which a rider rides; a rotary body which is rotatably supported on the vehicle body; a rotary body drive unit which rotatably drives the rotary body; and a control device which controls the rotary body drive unit for allowing the inverted pendulum type moving body to travel in accordance with a traveling instruction while keeping a balance, wherein the inverted pendulum type moving body further includes an uncontrollable state detection unit for detecting a state where the control of the inverted pendulum type moving body by the rider is highly improbable, and the control device stops a traveling of the inverted pendulum type moving body when the uncontrollable state is detected based on information detected by the uncontrollable state detection unit.

Abstract translation: 倒立式移动体。 倒立摆式移动体包括：具有骑乘者骑行的骑乘部的车身; 旋转体，其被可旋转地支撑在车身上; 旋转体驱动单元，其旋转地驱动旋转体; 以及控制装置，其控制所述旋转体驱动单元，用于允许所述倒立摆式移动体在保持平衡的同时根据行进指令行进，其中所述倒立摆式移动体还包括用于检测状态的不可控状态检测单元 其特征在于，所述骑乘者对倒立摆式移动体的控制是非常不可能的，并且当根据不可控状态检测单元检测到的信息检测到不可控状态时，控制装置停止倒立摆式移动体的行进。

公开(公告)号：US07623382B2

公开(公告)日：2009-11-24

申请号：US11649816

申请日：2007-01-05

Applicant: Chi Yuan Mou ,  Chien Hao Lu ,  Wen Pin Hsieh ,  Ya Chun Chang

Inventor： Chi Yuan Mou ,  Chien Hao Lu ,  Wen Pin Hsieh ,  Ya Chun Chang

IPC: G11C11/34 ,  G11C16/04 ,  G11C8/00

CPC classification number: G11C8/10

Abstract: A semiconductor memory and address-decoding circuit and method for decoding address allow the semiconductor memory to operate under a decreased capacity by disabling or hiding a predetermined portion of the semiconductor memory. The semiconductor memory has a first address-inputting circuit configured to receive a first external address, a switching circuit configured to switch a predetermined portion of the first external address to form an internal address, at least one address-setting code configured to set at least one predetermined bit of the internal address, a decoder coupling to the switching circuit and the address-setting code, and a memory array coupling to the decoder, wherein the decoder is configured to select at least one memory unit of the memory array based on the internal address. The first address-inputting circuit, the switching circuit and the address-setting code can be considered as an address-decoding circuit.

Abstract translation: 用于解码地址的半导体存储器和地址解码电路和方法允许半导体存储器通过禁止或隐藏半导体存储器的预定部分而在降低的容量下工作。 所述半导体存储器具有被配置为接收第一外部地址的第一地址输入电路，被配置为切换所述第一外部地址的预定部分以形成内部地址的开关电路，至少一个地址设置码被配置为至少设置 内部地址的一个预定位，耦合到开关电路的解码器和地址设置代码，以及耦合到解码器的存储器阵列，其中解码器被配置为基于该解码器选择存储器阵列的至少一个存储器单元 内部地址 第一地址输入电路，开关电路和地址设定码可以被认为是地址解码电路。

公开(公告)号：US20070148637A1

公开(公告)日：2007-06-28

申请号：US11318907

申请日：2005-12-27

Applicant: Ya-Chun Chang ,  Yueh-Chwen Hsu ,  Tze-Jung Yeh

Inventor： Ya-Chun Chang ,  Yueh-Chwen Hsu ,  Tze-Jung Yeh

IPC: C12Q1/70 ,  C12Q1/68 ,  C07H21/04

CPC classification number: C12Q1/701 ,  C12Q1/6895

Abstract: The inventions provides a method for identifying a target virus in an infected subject comprising the steps of designing a pair of degenerate primers corresponding to highly conserved regions of the target virus; designing a pair of species-specific primers according to highly variable sequences within the conserved regions of the target virus; preparing the species-specific probes according to the larger sequence variations within the conserved regions of the target virus, which are amplified with the species-specific primers as obtained; preparing a test sample by amplifying total nucleic acid of the infected subject with the degenerate primers as obtained; contacting the test sample with the species-specific probes as obtained; and detecting a hybridization between the species-specific probe and the test sample, wherein the hybridization indicates the target virus is identified in the infected subject. The primers and probes for detecting a garget virus are also provided.

Abstract translation: 本发明提供了一种用于鉴定感染对象中的靶病毒的方法，包括以下步骤：设计对应于目标病毒的高度保守区域的简并引物对; 根据目标病毒保守区域内高度可变序列设计一对物种特异性引物; 根据目标病毒保守区域内较大的序列变异制备物种特异性探针，其用获得的物种特异性引物扩增; 通过用所得的简并引物扩增感染受试者的总核酸来制备测试样品; 使测试样品与获得的物种特异性探针接触; 并检测物种特异性探针和测试样品之间的杂交，其中杂交表明在感染的受试者中鉴定出靶病毒。 还提供了用于检测靶标病毒的引物和探针。