公开(公告)号：US08674501B2

公开(公告)日：2014-03-18

申请号：US12659462

申请日：2010-03-09

申请人： Yasuhide Sosogi

发明人： Yasuhide Sosogi

IPC分类号： H01L23/498

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C2029/1206 ,  H01L23/5286 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.

摘要翻译： 半导体集成电路器件包括多个电路单元，每个电路单元具有多个逻辑电路; 以及从外部向半导体集成电路装置供电的多个电源端子，其中，具有多个逻辑电路的多个电路单元具有相互具有共同的封装设计，以及各电路单元的垂直方向和横向的长度 具有多个逻辑电路等于彼此相邻的电源端子之间的距离的偶数倍。

公开(公告)号：US20100329069A1

公开(公告)日：2010-12-30

申请号：US12818600

申请日：2010-06-18

申请人： Gaku Ito ,  Yousuke Kawashima ,  Yasuhide Sosogi ,  Satofumi Honda

发明人： Gaku Ito ,  Yousuke Kawashima ,  Yasuhide Sosogi ,  Satofumi Honda

IPC分类号： G11C8/10 ,  G11C8/00

CPC分类号： G11C11/418 ,  G11C8/08 ,  G11C8/10

摘要： A semiconductor memory device includes a plurality of memory cells that respectively stores data, a comparator that compares a row address in a previous cycle with a row address in a current cycle, and outputs a control signal to the row address decoder when the comparator detects a matching of a row address in a previous cycle and a row address in a current cycle, and a row address decoder that decodes the row address, and outputs a word line select signal to select one of word lines connected to a part of the plurality of memory cells based on the decoded row address, and prevents the output of the word line select signal when the control signal outputted from the comparator is inputted to the row address decoder.

摘要翻译： 半导体存储器件包括分别存储数据的多个存储器单元，将前一周期中的行地址与当前周期中的行地址进行比较的比较器，并且当比较器检测到一个时，输出控制信号到行地址解码器 前一周期中的行地址和当前周期中的行地址的匹配，以及对行地址进行解码的行地址解码器，并输出字线选择信号，以选择连接到多个 基于解码行地址的存储单元，并且当从比较器输出的控制信号输入到行地址解码器时，防止字线选择信号的输出。

公开(公告)号：US20100164099A1

公开(公告)日：2010-07-01

申请号：US12659462

申请日：2010-03-09

申请人： Yasuhide Sosogi

发明人： Yasuhide Sosogi

IPC分类号： H01L23/498 ,  G06F17/50

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C2029/1206 ,  H01L23/5286 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device includes plural circuit units each having plural logic circuits; and plural power terminals supplying power source from outside to the semiconductor integrated circuit device, in which the plural circuit units each having plural logic circuits have common packaging design with each other, and lengths in a vertical direction and a lateral direction of the circuit units each having plural logic circuits are equal to an even multiple of a distance between the power terminals adjacent to each other.

摘要翻译： 半导体集成电路器件包括多个电路单元，每个电路单元具有多个逻辑电路; 以及从外部向半导体集成电路装置供电的多个电源端子，其中，具有多个逻辑电路的多个电路单元具有相互具有共同的封装设计，以及各电路单元的垂直方向和横向的长度 具有多个逻辑电路等于彼此相邻的电源端子之间的距离的偶数倍。

公开(公告)号：US20090240900A1

公开(公告)日：2009-09-24

申请号：US12397672

申请日：2009-03-04

申请人： Yasuhide Sosogi ,  Kenji Ijitsu ,  Seiji Murata

发明人： Yasuhide Sosogi ,  Kenji Ijitsu ,  Seiji Murata

IPC分类号： G06F12/00

CPC分类号： G11C7/18 ,  G06F12/0893 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  Y02D10/13

摘要： A memory includes a plurality of blocks that each include a plurality of memory cell arrays connected to divided bit lines, a first decoder that generates a block select signal for selecting any of the blocks based on an inputted address signal, read/write portions disposed for the respective blocks, each of the read/write portions executes read or write of the memory cell array belonging to the block of its own, and signal generation portions each generates an operation control signal for bringing the read/write portion that belongs to the selected block into an operating state when the block thereof has been selected by the block select signal. Each of the signal generation portions generates an operation control signal for bringing the read/write portion that belongs to the block thereof into a non-operating state when the block thereof is not selected by the block select signal.

摘要翻译： 存储器包括多个块，每个块包括连接到划分的位线的多个存储单元阵列，第一解码器，其基于输入的地址信号产生用于选择任何块的块选择信号;第一解码器， 相应的块，每个读/写部分执行属于其自己的块的存储单元阵列的读或写，并且信号生成部分各自生成用于使属于所选择的读/写部分的读/写部分的操作控制信号 当其块被块选择信号选择时，该块成为操作状态。 每个信号产生部分当其块未被块选择信号选择时，产生用于使属于其块的读/写部分处于非操作状态的操作控制信号。