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公开(公告)号：US07430134B2
公开(公告)日：2008-09-30
申请号：US11676821
申请日：2007-02-20
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and second write buffer transistors to the latch circuit which stores data and the path is controlled by use of a word line and data write bit lines. Further, a read path is formed by connecting a read driver transistor and read transfer gate to the latch circuit and the path is controlled by use of the word line, read bit line and data of the latch circuit.
摘要翻译： 公开了一种包括锁存电路，第一和第二写入传输门，第一和第二写缓冲晶体管，读驱动晶体管和读传输门的SRAM。 通过将第一和第二写入传输门和第一和第二写入缓冲晶体管连接到存储数据的锁存电路并且通过使用字线和数据写入位线来控制路径来形成写入路径。 此外，通过将读驱动晶体管和读传输门连接到锁存电路来形成读路径，并且通过使用字线，读位线和锁存电路的数据来控制路径。
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公开(公告)号：US20060023553A1
公开(公告)日：2006-02-02
申请号：US10952824
申请日：2004-09-30
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C7/18 , H01L27/11 , H01L27/1104
摘要： A semiconductor device having hierarchized bit lines including an upper-layer bit line and a lower-layer bit line, includes at least one memory cell array to which the lower-layer bit line is connected and a selection transfer gate having an NMOS switching transistor and a PMOS switching transistor to connect the lower-layer bit line to the upper-layer bit line. The NMOS switching transistor and the PMOS switching transistor of the selection transfer gate are arranged opposite to each other in a column direction to sandwich the memory cell array.
摘要翻译： 具有包括上层位线和下层位线的层次化位线的半导体器件包括连接下层位线的至少一个存储单元阵列和具有NMOS开关晶体管的选择传输门，以及 用于将下层位线连接到上层位线的PMOS开关晶体管。 选择传输门的NMOS开关晶体管和PMOS开关晶体管在列方向上彼此相对布置以夹持存储单元阵列。
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公开(公告)号：US08072798B2
公开(公告)日：2011-12-06
申请号：US12496844
申请日：2009-07-02
申请人： Yasuhisa Takeyama
发明人： Yasuhisa Takeyama
IPC分类号： G11C11/00 , G11C11/412
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/1104
摘要： The semiconductor memory device includes: an inverter pair of a cross-coupled first and second inverters; a first transfer transistor including a front gate and a back gate connected to a first node to which an output terminal of the first inverter and an input terminal of the second inverter are connected; a second transfer transistor including a front gate and a back gate connected to a second node to which an output terminal of the second inverter and an input terminal of the first inverter are connected; a driver transistor whose gate is connected to the second node; and a read transistor including a front gate, a back gate connected to the second node, and a current path whose one end is connected to one end of a current path of the driver transistor.
摘要翻译： 半导体存储器件包括：交叉耦合的第一和第二反相器的反相器对; 第一转移晶体管，包括连接到第一反相器的输出端子和第二反相器的输入端子的第一节点连接的前栅极和后栅极; 第二传输晶体管，包括连接到第二反相器的输出端和第一反相器的输入端的第二节点连接的前栅极和后栅极; 栅极连接到第二节点的驱动晶体管; 以及读取晶体管，其包括前栅极，连接到第二节点的背栅极和电流路径，其一端连接到驱动晶体管的电流路径的一端。
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公开(公告)号：US20100302831A1
公开(公告)日：2010-12-02
申请号：US12790497
申请日：2010-05-28
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C11/412
摘要： A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.
摘要翻译： 静态随机存取存储器（SRAM）的存储单元包括一对驱动晶体管，一对负载晶体管，一对只写转移晶体管，一对只读传输晶体管，一对只读驱动器 晶体管和一对列选择晶体管。 存储单元还包括字线，一对写位线，一对读位线和列选择线。
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公开(公告)号：US08223579B2
公开(公告)日：2012-07-17
申请号：US12790497
申请日：2010-05-28
CPC分类号： G11C7/18 , G11C11/412
摘要： A memory cell of a static random access memory (SRAM) includes a pair of drive transistors, a pair of load transistors, a pair of write-only transfer transistors, a pair of read-only transfer transistors, a pair of read-only drive transistors, and a pair of column selection transistors. The memory cell also includes a word line, a pair of write bit lines, a pair of read bit lines, and a column selection line.
摘要翻译： 静态随机存取存储器（SRAM）的存储单元包括一对驱动晶体管，一对负载晶体管，一对只写转移晶体管，一对只读传输晶体管，一对只读驱动器 晶体管和一对列选择晶体管。 存储单元还包括字线，一对写位线，一对读位线和列选择线。
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公开(公告)号：US20100002496A1
公开(公告)日：2010-01-07
申请号：US12496844
申请日：2009-07-02
申请人： Yasuhisa Takeyama
发明人： Yasuhisa Takeyama
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/1104
摘要： The semiconductor memory device includes: an inverter pair of a cross-coupled first and second inverters; a first transfer transistor including a front gate and a back gate connected to a first node to which an output terminal of the first inverter and an input terminal of the second inverter are connected; a second transfer transistor including a front gate and a back gate connected to a second node to which an output terminal of the second inverter and an input terminal of the first inverter are connected; a driver transistor whose gate is connected to the second node; and a read transistor including a front gate, a back gate connected to the second node, and a current path whose one end is connected to one end of a current path of the driver transistor.
摘要翻译： 半导体存储器件包括：交叉耦合的第一和第二反相器的反相器对; 第一转移晶体管，包括连接到第一反相器的输出端子和第二反相器的输入端子的第一节点连接的前栅极和后栅极; 第二传输晶体管，包括连接到第二反相器的输出端和第一反相器的输入端的第二节点连接的前栅极和后栅极; 栅极连接到第二节点的驱动晶体管; 以及读取晶体管，其包括前栅极，连接到第二节点的背栅极和电流路径，其一端连接到驱动晶体管的电流路径的一端。
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公开(公告)号：US20070194833A1
公开(公告)日：2007-08-23
申请号：US11676821
申请日：2007-02-20
IPC分类号： H03K17/687
CPC分类号： G11C11/412
摘要： Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and second write buffer transistors to the latch circuit which stores data and the path is controlled by use of a word line and data write bit lines. Further, a read path is formed by connecting a read driver transistor and read transfer gate to the latch circuit and the path is controlled by use of the word line, read bit line and data of the latch circuit.
摘要翻译： 公开了一种包括锁存电路，第一和第二写入传输门，第一和第二写缓冲晶体管，读驱动晶体管和读传输门的SRAM。 通过将第一和第二写入传输门和第一和第二写入缓冲晶体管连接到存储数据的锁存电路并且通过使用字线和数据写入位线来控制路径来形成写入路径。 此外，通过将读驱动晶体管和读传输门连接到锁存电路来形成读路径，并且通过使用字线，读位线和锁存电路的数据来控制路径。
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公开(公告)号：US07259977B2
公开(公告)日：2007-08-21
申请号：US10952824
申请日：2004-09-30
CPC分类号： G11C11/412 , G11C7/18 , H01L27/11 , H01L27/1104
摘要： A semiconductor device having hierarchized bit lines including an upper-layer bit line and a lower-layer bit line, includes at least one memory cell array to which the lower-layer bit line is connected and a selection transfer gate having an NMOS switching transistor and a PMOS switching transistor to connect the lower-layer bit line to the upper-layer bit line. The NMOS switching transistor and the PMOS switching transistor of the selection transfer gate are arranged opposite to each other in a column direction to sandwich the memory cell array.
摘要翻译： 具有包括上层位线和下层位线的层次化位线的半导体器件包括连接下层位线的至少一个存储单元阵列和具有NMOS开关晶体管的选择传输门，以及 用于将下层位线连接到上层位线的PMOS开关晶体管。 选择传输门的NMOS开关晶体管和PMOS开关晶体管在列方向上彼此相对布置以夹持存储单元阵列。
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9.发明授权Driving device of charge pump circuit and driving pulse generation method thereof 失效电荷泵电路的驱动装置及其驱动脉冲产生方法
公开(公告)号：US5734286A
公开(公告)日：1998-03-31
申请号：US245770
申请日：1994-05-18
CPC分类号： H02M3/073 , H03K5/15013 , H03K5/1515 , H03K5/1565
摘要： A semiconductor circuit device includes an oscillator for outputting an oscillating signal, a driving signal generator for generating driving signals having respective phases based on a counting of oscillations of the oscillating signal, and a charge pump circuit driven by the driving signals. A pulse width ratio of the driving signals to one another is constant even when an oscillation period of the oscillating signal output by the oscillator changes, whereby the charge pump operates properly under changing conditions.
摘要翻译： 半导体电路装置包括用于输出振荡信号的振荡器，用于产生基于对振荡信号的振荡的计数的各相的驱动信号的驱动信号发生器和由驱动信号驱动的电荷泵电路。 即使当由振荡器输出的振荡信号的振荡周期改变时，驱动信号的脉冲宽度比也是恒定的，从而在变化的条件下电荷泵正常工作。
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