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1.发明授权Driving device of charge pump circuit and driving pulse generation method thereof 失效电荷泵电路的驱动装置及其驱动脉冲产生方法
公开(公告)号：US5734286A
公开(公告)日：1998-03-31
申请号：US245770
申请日：1994-05-18
CPC分类号： H02M3/073 , H03K5/15013 , H03K5/1515 , H03K5/1565
摘要： A semiconductor circuit device includes an oscillator for outputting an oscillating signal, a driving signal generator for generating driving signals having respective phases based on a counting of oscillations of the oscillating signal, and a charge pump circuit driven by the driving signals. A pulse width ratio of the driving signals to one another is constant even when an oscillation period of the oscillating signal output by the oscillator changes, whereby the charge pump operates properly under changing conditions.
摘要翻译： 半导体电路装置包括用于输出振荡信号的振荡器，用于产生基于对振荡信号的振荡的计数的各相的驱动信号的驱动信号发生器和由驱动信号驱动的电荷泵电路。 即使当由振荡器输出的振荡信号的振荡周期改变时，驱动信号的脉冲宽度比也是恒定的，从而在变化的条件下电荷泵正常工作。
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2.发明授权Read circuit of semiconductor and read method using a self-reference sensing technique 失效使用自参考感测技术的半导体读取电路和读取方法公开(公告)号：US07102945B2
公开(公告)日：2006-09-05
申请号：US11014862
申请日：2004-12-20
IPC分类号： G11C7/00
CPC分类号： G11C11/16 , G11C7/06 , G11C7/1051 , G11C7/1069 , G11C7/12 , G11C11/1673 , G11C2207/005
摘要： A read circuit of a semiconductor memory according to the present invention is based on a self-reference sensing technique by which data stored in a memory cell is determined by first and second signals read out from a memory cell through first and second read operations. This read circuit includes a sense amplifier which determines the data stored in the memory cell based on a potential of an input node, a transfer transistor which is connected between the memory cell and the input node, a precharge circuit which sets the input node to a precharge potential, and a VBIAS generator which turns the transfer transistor cutoff based on the first signal.
摘要翻译： 根据本发明的半导体存储器的读取电路基于自参考感测技术，通过第一和第二读取操作从存储器单元读出的第一和第二信号确定存储单元中存储的数据。 该读取电路包括读出放大器，其基于输入节点的电位确定存储在存储器单元中的数据，连接在存储单元和输入节点之间的传输晶体管，将输入节点设置为 预充电电位，以及基于第一信号使转移晶体管截止的VBIAS发生器。
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公开(公告)号：US06795334B2
公开(公告)日：2004-09-21
申请号：US10180024
申请日：2002-06-27
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C11/5607
摘要： A read blocks are connected to a read bit line. The read block has MTJ elements connected in series or in parallel, or arranged by combining series and parallel connections between the read bit line and a ground terminal. The MTJ elements are stacked on a semiconductor substrate. The read bit line is arranged on the MTJ elements stacked. A write word line extending in the X-direction and a write bit line extending in the Y-direction are present near the MTJ elements in the read block.
摘要翻译： 一个读块连接到读位线。 读块具有串联或并联连接的MTJ元件，或通过组合读位线与接地端之间的串联和并联连接进行排列。 MTJ元件堆叠在半导体衬底上。 读取位线被布置在堆叠的MTJ元件上。 在读取块中的MTJ元素附近存在沿X方向延伸的写字线和在Y方向上延伸的写位线。
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公开(公告)号：US5610859A
公开(公告)日：1997-03-11
申请号：US404572
申请日：1995-03-15
IPC分类号： G11C16/06 , G11C7/00 , G11C16/02 , G11C16/04 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C11/34
CPC分类号： G11C16/3477 , G11C16/10 , G11C16/3445 , G11C16/3459 , G11C16/3468 , G11C16/3486 , G11C7/00
摘要： A semiconductor memory device according to the invention comprises a semiconductor substrate, a memory cell array having memory cells, each of which stores data, formed in matrix on the semiconductor substrate, a plurality of data latch circuits, each of which is arranged a one end of at least one bit line connected to the memory cell array and for latching programming data, control section for judging whether all of a plurality of latched data included in data latch groups constituted by the plurality of data latch circuits are the same as a first data or not and for controlling to change a potential of a plurality of first nodes according to the judging result, where there is one first node corresponding to each data latch circuit group, section for detecting potentials of the plurality of the first nodes corresponding to the plurality of data latch circuit groups, judging whether all data latched by the latch circuits includes in the plurality of latch circuit groups are the same as the first data and for controlling to change a potential of a plurality of second nodes according to the judging result, and section for detecting the potential of the plurality of second nodes and for outputting a judging result whether all of data latched by data latch circuits, which are included in the plurality of the data latch circuit groups, are the same as the first data or not.
摘要翻译： 根据本发明的半导体存储器件包括半导体衬底，具有存储单元的存储单元阵列，每个存储器单元存储矩阵形成在半导体衬底上的数据，多个数据锁存电路，每个数据锁存电路布置成一端 连接到存储单元阵列的至少一个位线和用于锁存编程数据的控制部分，用于判断包括在由多个数据锁存电路构成的数据锁存器组中的多个锁存数据是否与第一数据相同 并且用于根据判断结果控制多个第一节点的电位，其中存在对应于每个数据锁存电路组的一个第一节点，用于检测对应于多个第一节点的多个第一节点的电位的部分 的数据锁存电路组，判断由锁存电路锁存的所有数据是否包含在多个锁存电路组中是相同的 第一数据和用于根据判断结果控制多个第二节点的电位的变化，以及用于检测多个第二节点的电位的部分，并且用于输出由数据锁存电路锁存的所有数据的判断结果， 包含在多个数据锁存电路组中的数据与第一数据相同。
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5.发明授权Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5452249A
公开(公告)日：1995-09-19
申请号：US210434
申请日：1994-03-21
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor changes the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，并且晶体管改变位线。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点中的一个连接到预定电位，从而将触发电路设置为第二状态 在验证模式之前的状态。
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6.发明授权Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件
公开(公告)号：US5557568A
公开(公告)日：1996-09-17
申请号：US427265
申请日：1995-04-24
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，晶体管对位线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 一种数据设定电路，用于在触发电路的第一和第二信号节点之一连接到预定电位，当位线在验证模式下处于充电电位时，从而将触发器电路设置在第二状态，而与 在验证模式之前的状态。
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公开(公告)号：US07054188B2
公开(公告)日：2006-05-30
申请号：US11012178
申请日：2004-12-16
IPC分类号： G11C11/00
摘要： A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither perpendicular nor parallel to the magnetization easy axis direction of the MTJ elements. One and the other end of one first write line pass an upper or lower periphery of the memory cell array and a left or right periphery of the memory cell array, respectively. The first write lines and second write lines sandwich the MTJ elements. First write line drivers are connected to both ends of the first write lines, one and the other end of a pair of the first write line drivers connected to ends of one first write lines are located outside the upper or lower periphery and outside the left or right periphery, respectively. Second write line drivers are connected to both ends of the second write lines.
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公开(公告)号：US6023424A
公开(公告)日：2000-02-08
申请号：US213411
申请日：1998-12-17
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device comprises a flip-flop circuit for holding write data in one of first and second states, a bit line connected to the flip-flop circuit via a switching element, a transistor for charging the bit line, a non-volatile memory cell, connected to the bit line and having a MOS transistor structure, for storing data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode said threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range, and a data setting circuit for connecting one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
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公开(公告)号：US5880994A
公开(公告)日：1999-03-09
申请号：US909727
申请日：1997-08-12
申请人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
发明人： Junichi Miyamoto , Yasuo Itoh , Yoshihisa Iwata
IPC分类号： G11C17/00 , G11C7/02 , G11C7/10 , G11C16/02 , G11C16/06 , G11C16/10 , G11C16/34 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： G11C16/3459 , G11C16/10 , G11C16/3454 , G11C7/02 , G11C7/1006 , G11C7/1048
摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line and line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.
摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，晶体管对位线和线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与 在验证模式之前的状态。
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公开(公告)号：US20060056217A1
公开(公告)日：2006-03-16
申请号：US11012178
申请日：2004-12-16
IPC分类号： G11C5/06
摘要： A magnetic memory device includes a memory cell array including MTJ elements provided at the coordinates (x, y). First write lines extend in a direction neither perpendicular nor parallel to the magnetization easy axis direction of the MTJ elements. One and the other end of one first write line pass an upper or lower periphery of the memory cell array and a left or right periphery of the memory cell array, respectively. The first write lines and second write lines sandwich the MTJ elements. First write line drivers are connected to both ends of the first write lines, one and the other end of a pair of the first write line drivers connected to ends of one first write lines are located outside the upper or lower periphery and outside the left or right periphery, respectively. Second write line drivers are connected to both ends of the second write lines.
摘要翻译： 磁存储器件包括存储单元阵列，其包括在坐标（x，y）处提供的MTJ元件。 第一写入线在既不垂直也不平行于MTJ元件的易磁化轴方向的方向上延伸。 一个第一写入线的一端和另一端分别通过存储单元阵列的上周边或下周围以及存储单元阵列的左边缘或右边缘。 第一个写入行和第二个写入行夹着MTJ元素。 第一写入线驱动器连接到第一写入线的两端，连接到一个第一写入线的端部的一对第一写入线驱动器的一端和另一端位于左上方或下侧外侧， 右边缘。 第二写线驱动器连接到第二写线的两端。
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