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    Silicon substrate evaluation method and semiconductor device manufacturing method
    2.
    发明授权
    Silicon substrate evaluation method and semiconductor device manufacturing method 有权
    硅衬底评估方法和半导体器件制造方法

    公开(公告)号：US06187600B1

    公开(公告)日：2001-02-13

    申请号：US09175404

    申请日：1998-10-20

    申请人： Yoichi Fujisawa ,  Kaoru Ogawa ,  Kenichi Hikazutani

    发明人： Yoichi Fujisawa ,  Kaoru Ogawa ,  Kenichi Hikazutani

    IPC分类号： G01R3126

    CPC分类号： H01L22/24 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A surface layer portion of a silicon substrate is etched by using a mixed solution which contains ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O) at a weight ratio of 1:(1.3 to 2.65):(275 to 433). The density of the etch pits which have occurred in a surface of the silicon substrate whose surface layer portion was etched by the etching step is measured. The crystal quality, etc. of the silicon substrate are evaluated before a process for manufacturing semiconductor devices using such silicon substrates, in order to avoid a lowering of the yields of the semiconductor devices.

    摘要翻译： 使用含有氢氧化铵（NH 4 OH），过氧化氢（H 2 O 2）和水（H 2 O）的混合溶液，以1：（1.3〜2.65）：（275〜433）的比例蚀刻硅衬底的表层部分 ）。 测量在通过蚀刻步骤蚀刻表面层部分的硅衬底的表面中发生的蚀刻凹坑的密度。 在制造使用这种硅衬底的半导体器件的工艺之前，对硅衬底的晶体质量进行评估，以避免半导体器件的产量降低。

    COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFCTURING SAME
    3.
    发明申请
    COMPOUND SEMICONDUCTOR DEVICE AND METHOD OF MANUFCTURING SAME 有权
    化合物半导体器件及其制造方法

    公开(公告)号：US20110272742A1

    公开(公告)日：2011-11-10

    申请号：US13089981

    申请日：2011-04-19

    申请人： Shinichi AKIYAMA ,  Kenji Nukui ,  Mutsumi Katou ,  Yoshitaka Watanabe ,  Tetsuya Itou ,  Yoichi Fujisawa ,  Toshiya Sato ,  Tsutomu Hosoda ,  Yuuichi Satou

    发明人： Shinichi AKIYAMA ,  Kenji Nukui ,  Mutsumi Katou ,  Yoshitaka Watanabe ,  Tetsuya Itou ,  Yoichi Fujisawa ,  Toshiya Sato ,  Tsutomu Hosoda ,  Yuuichi Satou

    IPC分类号： H01L29/778 ,  H01L21/335

    CPC分类号： H01L29/778 ,  H01L21/324 ,  H01L29/1029 ,  H01L29/2003 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

    摘要： A compound semiconductor device includes a substrate; a compound semiconductor layer formed on the substrate; a first insulating film formed on the compound semiconductor layer; a second insulating film formed on the first insulating film; and a gate electrode, a source electrode, and a drain electrode, each being formed on the compound semiconductor layer, wherein the gate electrode is formed of a first opening filled with a first conductive material via at least a gate insulator, and the first opening is formed in the first insulating film and configured to partially expose the compound semiconductor layer, and wherein the source electrode and the drain electrode are formed of a pair of second openings filled with at least a second conductive material, and the second openings are formed in at least the second insulating film and the first insulating film and configured to partially expose the compound semiconductor layer.

    摘要翻译： 化合物半导体器件包括：衬底; 形成在所述基板上的化合物半导体层; 形成在所述化合物半导体层上的第一绝缘膜; 形成在所述第一绝缘膜上的第二绝缘膜; 以及栅电极，源电极和漏电极，各自形成在化合物半导体层上，其中栅电极由至少一栅极绝缘体填充有第一导电材料的第一开口形成，第一开口 形成在所述第一绝缘膜中并且被配置为部分地暴露所述化合物半导体层，并且其中所述源电极和所述漏电极由填充有至少第二导电材料的一对第二开口形成，并且所述第二开口形成在 至少所述第二绝缘膜和所述第一绝缘膜，并且被配置为部分地暴露所述化合物半导体层。

    Method of fabricating semiconductor devices using an intermediate grinding step
    4.
    发明授权
    Method of fabricating semiconductor devices using an intermediate grinding step 失效
    使用中间磨削步骤制造半导体器件的方法

    公开(公告)号：US5426073A

    公开(公告)日：1995-06-20

    申请号：US135577

    申请日：1993-10-13

    申请人： Kazunori Imaoka ,  Yoichi Fujisawa

    发明人： Kazunori Imaoka ,  Yoichi Fujisawa

    IPC分类号： B24B9/06 ,  H01L21/304 ,  H01L21/306 ,  H01L21/00 ,  H01L21/02 ,  H01L21/302 ,  H01L21/463

    CPC分类号： H01L21/306 ,  B24B9/065 ,  H01L21/304

    摘要： In wafer processes, after at least one layer which constitutes a structural member of a functional semiconductor element is formed on a semiconductor wafer, a brittle, excessive deposition on an edge of the semiconductor wafer is removed by grinding or etching of the wafer edge until the underlying wafer is exposed. The removal of the excessive deposition on the wafer edge reduces dust generation caused from crack and peel-off of the excessive deposition on the wafer edge, even if the wafer edge contacts a jig, and the like. Thus, the reduction in dust generation improves production yields of highly integrated semiconductor devices.

    摘要翻译： 在晶片工艺中，在半导体晶片上形成至少一层构成功能性半导体元件的结构部件的层之后，通过研磨或蚀刻晶片边缘来去除在半导体晶片的边缘上的脆性，过度沉积，直到 下面的晶片被暴露。 去除晶片边缘上的过度沉积减少了由于晶片边缘上的过度沉积而导致的由于裂纹和剥离引起的灰尘产生，即使晶片边缘接触夹具等。 因此，减少粉尘产生提高了高度集成的半导体器件的生产率。