公开(公告)号：US06833589B2

公开(公告)日：2004-12-21

申请号：US10075588

申请日：2002-02-15

申请人： Hideaki Matsuhashi ,  Yoko Kajita ,  Yoshihiro Koga ,  Toshiyuki Nakamura ,  Jun Kanamori

发明人： Hideaki Matsuhashi ,  Yoko Kajita ,  Yoshihiro Koga ,  Toshiyuki Nakamura ,  Jun Kanamori

IPC分类号： H01L29360

CPC分类号： H01L29/66772 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/78612 ,  H01L29/78621 ,  H01L29/78654

摘要： A field oxide film for element isolation is formed on an SOI substrate having a silicon layer formed on an insulating layer, an active nitride film is wet-etched to reduce its film thickness to a value small enough to allow the edge of the silicon layer to become exposed and ions of a channel stopping impurity are implanted only into the edge of the silicon layer through self-alignment either vertically or at an angle by using the active nitride film as a mask. Through this manufacturing method, a field effect transistor which achieves a small gate length, is free from the adverse effect of a parasitic transistor and thus does not readily manifest a hump, and allows a reduction in the distance between an nMOS and a pMOS provided next to each other is realized.

摘要翻译： 用于元件隔离的场氧化膜形成在具有形成在绝缘层上的硅层的SOI衬底上，湿蚀刻活性氮化物膜以将其膜厚度减小到足以允许硅层的边缘 通过使用活性氮化物膜作为掩模，通过垂直或以一定角度的自对准将植入杂质的沟道的离子仅注入硅层的边缘。 通过这种制造方法，实现小栅极长度的场效应晶体管没有寄生晶体管的不利影响，因此不容易发现隆起，并且允许减小nMOS和下一个提供的pMOS之间的距离 相互实现。

公开(公告)号：US20060065917A1

公开(公告)日：2006-03-30

申请号：US11228188

申请日：2005-09-19

申请人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

发明人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/11507

摘要： A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

摘要翻译： 一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层 覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。

公开(公告)号：US07579640B2

公开(公告)日：2009-08-25

申请号：US11228188

申请日：2005-09-19

申请人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

发明人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

IPC分类号： H01L27/115

CPC分类号： H01L27/11502 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/11507

摘要： A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

摘要翻译： 一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层 覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。

公开(公告)号：US06833295B2

公开(公告)日：2004-12-21

申请号：US10630869

申请日：2003-07-31

申请人： Yoko Kajita

发明人： Yoko Kajita

IPC分类号： H01L21336

CPC分类号： H01L29/78696 ,  H01L29/665 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66613 ,  H01L29/66772 ,  H01L29/78618

摘要： An oxidation process is performed for a surface of the SOI film exposed from the opening pattern to form and eliminate the silicon oxide film, so that the SOI film would be thinned. In the opening pattern, formed a gate oxide film as a third insulation film, on which a poly-silicon film is formed as a conductive film so as to fill in the opening pattern. The first insulation film is then eliminated while the second insulation film formed on the inner wall of the opening pattern is remained, so that a gate electrode provided on the side wall thereof with a sidewall would be formed on the gate oxide film.