公开(公告)号：US20060065917A1

公开(公告)日：2006-03-30

申请号：US11228188

申请日：2005-09-19

申请人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

发明人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

IPC分类号： H01L29/94

CPC分类号： H01L27/11502 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/11507

摘要： A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

摘要翻译： 一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层 覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。

公开(公告)号：US07579640B2

公开(公告)日：2009-08-25

申请号：US11228188

申请日：2005-09-19

申请人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

发明人： Yoko Kajita ,  Ichiro Koiwa ,  Takao Kanehara ,  Kinya Ashikaga ,  Kazuhide Abe

IPC分类号： H01L27/115

CPC分类号： H01L27/11502 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/11507

摘要： A hybrid memory device includes a plurality of regions including a memory cell array region upon which are formed a plurality of memory cells and a logic circuit region upon which is formed a logic circuit device, and is provided with a liner oxide layer formed on a region covering the logic circuit region except the memory cell array region and a cover layer formed on the liner oxide layer while extending to the memory cell array region.

摘要翻译： 一种混合存储器件包括多个区域，包括形成有多个存储单元的存储单元阵列区域和形成逻辑电路器件的逻辑电路区域，并且在其上形成有衬底氧化物层 覆盖除了存储单元阵列区域之外的逻辑电路区域和形成在衬垫氧化物层上的覆盖层，同时延伸到存储单元阵列区域。

公开(公告)号：US08305147B2

公开(公告)日：2012-11-06

申请号：US13424591

申请日：2012-03-20

申请人： Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya

发明人： Tadahiro Sasaki ,  Kazuhide Abe ,  Kazuhiko Itaya

IPC分类号： H03F3/14

CPC分类号： H03F3/19 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/41758 ,  H01L29/4238 ,  H03F3/245

摘要： A power amplifier according to the embodiments includes: a silicon substrate; an input terminal configured to receive an input of a RF signal; a power dividing unit configured to divide the RF signal into a first signal and a second signal; a phase modulating unit configured to modulate a phase of the second signal; an N well formed in the silicon substrate; a P well formed in the N well and configured to receive an input of the second signal of a modulated phase; a gate insulating film formed on the P well; a gate electrode formed on the gate insulating film and configured to receive an input of the first signal; source and drain electrodes formed on both sides of the gate electrode in the silicon substrate; and an output terminal configured to output a RF signal obtained from the drain electrode.

摘要翻译： 根据实施例的功率放大器包括：硅衬底; 输入终端，被配置为接收RF信号的输入; 功率分配单元，被配置为将RF信号划分为第一信号和第二信号; 相位调制单元，被配置为调制所述第二信号的相位; 在硅衬底中形成N阱; P阱形成在N阱中并且被配置为接收调制相位的第二信号的输入; 在P阱上形成栅极绝缘膜; 栅电极，形成在所述栅极绝缘膜上并被配置为接收所述第一信号的输入; 源极和漏极形成在硅衬底中的栅电极的两侧; 以及输出端子，被配置为输出从漏电极获得的RF信号。

公开(公告)号：US08039873B2

公开(公告)日：2011-10-18

申请号：US12276787

申请日：2008-11-24

申请人： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya

发明人： Kazuhide Abe ,  Tadahiro Sasaki ,  Kazuhiko Itaya

IPC分类号： H01L27/105

CPC分类号： H01L27/088 ,  H01L23/4824 ,  H01L27/0207 ,  H01L27/105 ,  H01L29/1033 ,  H01L29/41758 ,  H01L29/7831 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes a substrate including an element region having a polygonal shape defined by a plurality of edges, and an isolation region surrounding the element region, and a plurality of gate electrodes provided on the substrate, crossing the element region, arranged in parallel with each other, and electrically connected with each other, wherein at least one of the edges does not cross any of the gate electrodes, and is not parallel to the gate electrodes.

摘要翻译： 半导体器件包括：衬底，其包括具有由多个边缘限定的多边形形状的元件区域和围绕该元件区域的隔离区域;以及多个栅电极，设置在该衬底上，与该元件区域交叉，与该 彼此电连接，其中至少一个边缘不与任何栅电极交叉，并且不平行于栅电极。

公开(公告)号：US20110039359A1

公开(公告)日：2011-02-17

申请号：US12923949

申请日：2010-10-15

申请人： Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

发明人： Isao Takasu ,  Yuko Nomura ,  Tsuyoshi Hioki ,  Isao Amemiya ,  Kazuhide Abe

IPC分类号： H01L33/48

CPC分类号： H01L33/54 ,  H01L33/46 ,  H01L33/507 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of manufacturing a light emitting device. The method includes: mounting a light emitting chip on a substrate; forming a transparent resin portion and a phosphor layer by using a liquid droplet discharging apparatus, the transparent resin portion being formed in a shape of a dome and covering the light emitting chip to fill an exterior thereof on the substrate, a phosphor layer containing phosphor and being formed on an exterior of the transparent resin portion close to at least a top side thereof; and forming a reflecting layer at a position exterior of the transparent resin portion and the phosphor layer close to the substrate.

摘要翻译： 一种制造发光器件的方法。 该方法包括：将发光芯片安装在基板上; 通过使用液滴喷射装置形成透明树脂部分和荧光体层，所述透明树脂部分形成为圆顶形状并且覆盖所述发光芯片以将其外部填充在所述基板上，所述荧光体层包含磷光体和 形成在透明树脂部分的至少其顶侧附近的外部; 并且在透明树脂部分的外部和靠近基板的荧光体层的位置处形成反射层。

公开(公告)号：US07769352B2

公开(公告)日：2010-08-03

申请号：US11568365

申请日：2006-09-25

申请人： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

发明人： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

IPC分类号： H04B1/40 ,  H04B7/00 ,  H04L27/22

CPC分类号： H04L27/2272 ,  H03C3/0966 ,  H03D3/242 ,  H04B1/38 ,  H04L27/2273 ,  H04L2027/0016 ,  H04L2027/0022 ,  H04L2027/0055 ,  H04W56/00 ,  H04W88/02 ,  Y02D70/1222 ,  Y02D70/40

摘要： A receiver has a first voltage control oscillator configured to generate a first oscillation signal, a second voltage control oscillator configured to generate a second oscillation signal having a first phase, a first phase comparator configured to detect a phase difference between the first and second oscillation signals, a demodulator configured to perform demodulation processing of the received signal and to generate timing information of a second phase included in the first oscillation signal, a second phase comparator configured to detect the phase difference between the first and second oscillation signals, and a first control voltage generator configured to generate a first control voltage for controlling a phase and a frequency of the second voltage control oscillator based on the phase difference detected by the second phase comparator.

摘要翻译： 一种接收器具有：第一电压控制振荡器，被配置为产生第一振荡信号;第二压控振荡器，被配置为产生具有第一相位的第二振荡信号;第一相位比较器，被配置为检测第一和第二振荡信号之间的相位差; 解调器，被配置为执行所述接收信号的解调处理并生成包括在所述第一振荡信号中的第二相位的定时信息;第二相位比较器，被配置为检测所述第一和第二振荡信号之间的相位差;以及第一控制 电压发生器被配置为基于由第二相位比较器检测的相位差产生用于控制第二压控振荡器的相位和频率的第一控制电压。

公开(公告)号：US07718515B2

公开(公告)日：2010-05-18

申请号：US12073492

申请日：2008-03-06

申请人： Kazuhide Abe

发明人： Kazuhide Abe

IPC分类号： H01L21/20

CPC分类号： H01L29/66712 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3225 ,  H01L29/1608 ,  H01L29/66068

摘要： The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer.

摘要翻译： 本发明的主要目的是提供能够减少晶片弯曲的半导体器件的结构以及制造半导体器件的方法。 本发明应用于半导体器件，其由具有碳化硅（SiC）膜的半导体衬底制造。 该方法包括以下步骤：在半导体晶片上形成SiC膜; 鉴别半导体晶片的变形状态; 以及在所述SiC膜中形成槽，所述槽具有根据所述半导体晶片的变形条件确定的形状。

公开(公告)号：US20080238550A1

公开(公告)日：2008-10-02

申请号：US11857737

申请日：2007-09-19

申请人： Tadahiro SASAKI ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Hideyuki Funaki

发明人： Tadahiro SASAKI ,  Kazuhide Abe ,  Kazuhiko Itaya ,  Hideyuki Funaki

IPC分类号： H03F3/16 ,  H03F3/68

CPC分类号： H03F3/604 ,  H01L21/823425 ,  H01L27/088 ,  H03F1/3205 ,  H03F3/16 ,  H03F3/607 ,  H03F3/72 ,  H03F2200/108 ,  H03F2200/451 ,  H03F2200/468 ,  H03F2200/543 ,  H03F2200/78 ,  H03F2203/7236

摘要： A power amplifier includes: a first multi-finger FET formed on a semiconductor substrate; a second multi-finger FET formed on the semiconductor substrate; a first temperature detector which detects a channel temperature of the first FET; a second temperature detector which detects a channel temperature of the second FET; a third temperature detector which detects a temperature of the semiconductor substrate; a first detection circuit detecting a difference between an output of the first temperature detector and an output of the third temperature detector and converting the difference to thermoelectromotive force; a second detection circuit detecting a difference between an output of the second temperature detector and the output of the third temperature detector and converting the difference to thermoelectromotive force; and a comparator comparing outputs of the first and second detection circuits with each other to turn on one of the first and second switches and turn off the other.

摘要翻译： 功率放大器包括：形成在半导体衬底上的第一多指FET; 形成在半导体衬底上的第二多指FET; 第一温度检测器，其检测第一FET的通道温度; 第二温度检测器，其检测第二FET的通道温度; 第三温度检测器，其检测半导体衬底的温度; 第一检测电路，检测第一温度检测器的输出和第三温度检测器的输出之间的差异，并将差值转换为热电动势; 第二检测电路，检测第二温度检测器的输出与第三温度检测器的输出之间的差异，并将差值转换为热电动势; 以及比较器，将第一和第二检测电路的输出彼此进行比较，以打开第一和第二开关中的一个并且关闭另一个。

公开(公告)号：US20080233716A1

公开(公告)日：2008-09-25

申请号：US12073492

申请日：2008-03-06

申请人： Kazuhide Abe

发明人： Kazuhide Abe

IPC分类号： H01L21/322

CPC分类号： H01L29/66712 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/3225 ,  H01L29/1608 ,  H01L29/66068

摘要： The principal objects of the present invention are to provide structure of a semiconductor device capable of reducing a bowing of a wafer, and a method for fabricating the semiconductor device. The present invention is applied to a semiconductor device, which is fabricated with a semiconductor substrate having a silicon carbide (SiC) film. The method includes the steps of: forming the SiC film on a semiconductor wafer; discriminating a deformation condition of the semiconductor wafer; and forming grooves in the SiC film, the grooves having a shape determined in accordance with the deformation condition of the semiconductor wafer.

摘要翻译： 本发明的主要目的是提供能够减少晶片弯曲的半导体器件的结构以及制造半导体器件的方法。 本发明应用于半导体器件，其由具有碳化硅（SiC）膜的半导体衬底制造。 该方法包括以下步骤：在半导体晶片上形成SiC膜; 鉴别半导体晶片的变形状态; 以及在所述SiC膜中形成槽，所述槽具有根据所述半导体晶片的变形条件确定的形状。

公开(公告)号：US07215066B2

公开(公告)日：2007-05-08

申请号：US11196596

申请日：2005-08-04

申请人： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

发明人： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

IPC分类号： H01L41/053

CPC分类号： H01H57/00 ,  H01G5/18 ,  H01G5/38 ,  H01H2057/006 ,  H01L41/094 ,  H01L41/0946 ,  H01L41/0953 ,  Y10S977/837

摘要： A piezoelectric actuator includes a first beam including a first bottom electrode, a first piezoelectric film on the first bottom electrode, and a first top electrode on the first piezoelectric film, a fixed end assigned at an end of the first beam and fixed on a substrate, a connecting end assigned at another end of the first beam and suspended over a free space; and a second beam including a second piezoelectric film connected to the first piezoelectric film at the connecting end, a second bottom electrode under the second piezoelectric film, and a second top electrode on the second piezoelectric film, a working end assigned at an end of the second beam opposite to another end to which the connecting end is assigned and suspended over the free space; wherein a distance between centers of the fixed end and the working end is shorter than a distance from the working end to the connecting end.

摘要翻译： 压电致动器包括第一梁，该第一梁包括第一底电极，第一底电极上的第一压电膜和第一压电膜上的第一顶电极，分配在第一梁的端部并固定在基板上的固定端 ，分配在第一梁的另一端并悬挂在自由空间上的连接端; 以及第二光束，包括在连接端连接到第一压电膜的第二压电膜，第二压电膜下的第二底电极和第二压电膜上的第二顶电极，分配在第二压电膜的端部的工作端 第二梁相对于连接端被分配并悬挂在自由空间上的另一端; 其中固定端和工作端的中心之间的距离短于从工作端到连接端的距离。