公开(公告)号：US20120015510A1

公开(公告)日：2012-01-19

申请号：US13186324

申请日：2011-07-19

申请人： Min Yong LEE ,  Yong Soo Jung

发明人： Min Yong LEE ,  Yong Soo Jung

IPC分类号： H01L21/425

CPC分类号： H01L21/26586 ,  H01L29/1045 ,  H01L29/1083

摘要： A method of fabricating a semiconductor device includes forming a mask pattern for defining a region of a semiconductor substrate. A field stop dopant layer will be formed in the defined region. Dopant ions are implanted into the defined region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.

摘要翻译： 制造半导体器件的方法包括形成用于限定半导体衬底的区域的掩模图案。 在限定的区域中将形成场阻挡掺杂剂层。 掺杂离子以约4.4°至7°的倾斜角度注入到半导体衬底的限定区域中。

公开(公告)号：US07687852B2

公开(公告)日：2010-03-30

申请号：US12371788

申请日：2009-02-16

申请人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

发明人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

IPC分类号： H01L29/76

CPC分类号： H01L29/1037 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.

摘要翻译： 具有凹槽的半导体器件及其制造方法。 半导体器件包括在其中形成有反三角形凹槽的半导体衬底; 在半导体衬底上形成具有指定厚度的栅极绝缘膜; 栅电极形成在栅极绝缘膜上，使得栅电极填充反三角形凹部并从半导体衬底的表面突出; 以及形成在半导体衬底中并且彼此相对的第一和第二接合区域，使得相应的一个栅电极插入其间。

公开(公告)号：US20100041196A1

公开(公告)日：2010-02-18

申请号：US12603906

申请日：2009-10-22

申请人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

发明人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/4236 ,  H01L21/26586 ,  H01L21/28061 ,  H01L29/1041 ,  H01L29/516 ,  H01L29/66621

摘要： A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.

摘要翻译： 具有凹陷栅极结构的晶体管及其制造方法。 晶体管包括形成在形成在半导体衬底中的第一沟槽的内壁上的栅极绝缘层; 形成在所述栅极绝缘层上以部分地填充所述第一沟槽的栅极导电层; 栅极电极，形成在栅极导电层上，用于完全填充第一沟槽，并被栅极导电层包围; 形成在半导体衬底中的第一沟槽区; 以及形成在半导体衬底的浅部中的源极/漏极区域。

公开(公告)号：US07576339B2

公开(公告)日：2009-08-18

申请号：US11445542

申请日：2006-06-02

申请人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Jung ,  Yong Soo Jung

发明人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Jung ,  Yong Soo Jung

IPC分类号： G21K5/10 ,  H01J37/08

CPC分类号： H01J37/3171 ,  H01J37/04 ,  H01J37/3023 ,  H01J2237/057 ,  H01J2237/30483 ,  H01J2237/31703

摘要： An ion implantation apparatus includes an ion beam source for generating an ion beam; an implantation energy controller disposed on a path of the ion beam for controlling the ion implantation energy of the ion beam so that an ion beam having a first implantation energy is created for a first period of time and an ion beam having a second implantation energy is created for a second period of time; a beam line for accelerating the ion beam; and an end station for mounting a substrate, into which the ion beam accelerated by the beam line is implanted onto the substrate.

摘要翻译： 离子注入装置包括用于产生离子束的离子束源; 植入能量控制器，设置在离子束的路径上，用于控制离子束的离子注入能量，使得具有第一注入能量的离子束产生第一时间段，并且具有第二注入能量的离子束是 创造了第二个时期; 用于加速离子束的束线; 以及用于安装衬底的终端站，其中通过射束线加速的离子束被注入到衬底上。

公开(公告)号：US07511337B2

公开(公告)日：2009-03-31

申请号：US11501943

申请日：2006-08-10

申请人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

发明人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

IPC分类号： H01L29/76

CPC分类号： H01L29/1037 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.

摘要翻译： 具有凹槽的半导体器件及其制造方法。 半导体器件包括在其中形成有反三角形凹槽的半导体衬底; 在半导体衬底上形成具有指定厚度的栅极绝缘膜; 栅电极形成在栅极绝缘膜上，使得栅电极填充反三角形凹部并从半导体衬底的表面突出; 以及形成在半导体衬底中并且彼此相对的第一和第二接合区域，使得相应的一个栅电极插入其间。

公开(公告)号：US20080158937A1

公开(公告)日：2008-07-03

申请号：US11771131

申请日：2007-06-29

申请人： Yong Soo Jung ,  Min Yong Lee

发明人： Yong Soo Jung ,  Min Yong Lee

IPC分类号： G11C11/24

CPC分类号： G11C11/24

摘要： Disclosed herein is a memory device having an increased level of integration with a simplified method of manufacture The memory device includes: a plurality of word lines and a plurality of bit lines each regularly arranged, and a plurality of unit memory cells each formed at an intersection between an associated one of the word lines and an associated one of the bit lines, wherein each unit memory cell includes a capacitor connected to one of the bit lines and a threshold voltage switching device comprising two terminals, one terminal being connected to the capacitor and the other terminal being connected to one of the bit lines, the threshold voltage switching device being capable of switching current flow at a specific threshold voltage via a rapid variation in resistance depending upon a voltage applied through the word line and the bit line, wherein the capacitor is capable of accumulating electric charges supplied from the bit line based on a switching operation of the threshold voltage switching device.

摘要翻译： 本文公开了一种具有与简化制造方法的集成度增加的存储器件。存储器件包括：多个字线和多个位线，每个位线都规则排列，并且多个单元存储单元分别形成在交叉点 其中每个单位存储单元包括连接到其中一个位线的电容器和包括两个端子的阈值电压开关器件，一个端子连接到电容器， 另一个端子连接到一个位线，阈值电压切换装置能够根据通过字线和位线施加的电压，经由电阻的快速变化来切换特定阈值电压的电流，其中， 电容器能够基于阈值的切换操作累积从位线提供的电荷 电压开关装置。

公开(公告)号：US20070187620A1

公开(公告)日：2007-08-16

申请号：US11423306

申请日：2006-06-09

申请人： Yong Soo Jung ,  Seung Woo Jin ,  Min Yong Lee ,  Kyoung Bong Rouh

发明人： Yong Soo Jung ,  Seung Woo Jin ,  Min Yong Lee ,  Kyoung Bong Rouh

IPC分类号： H01J37/08

CPC分类号： H01J37/3172 ,  H01J2237/31703 ,  H01J2237/31711

摘要： Disclosed herein is an apparatus and method for partial ion implantation. The apparatus includes a wafer support, an ion beam irradiator capable of generating and irradiating an ion beam entering the wafer, and an ion beam exposure adjustor to adjust exposure of the wafer with respect to the ion beam according to regions of the wafer by setting an exposure opening via combination of ion beam shields for blocking the ion beam with respect to the wafer. The exposure opening enables the wafer to be partially exposed to the ion beam irradiated therethrough. With this apparatus, effective partial ion implantation can be performed to compensate variation of a threshold voltage Vt in a channel of a transistor, thereby providing more uniform characteristics of the transistor.

摘要翻译： 本文公开了一种用于部分离子注入的装置和方法。 该装置包括晶片支撑件，能够产生和照射进入晶片的离子束的离子束照射器和离子束曝光调节器，用于根据晶片的区域调整晶片相对于离子束的曝光， 通过离子束屏蔽的组合来暴露开口，用于阻挡离子束相对于晶片。 曝光开口使得晶片能够部分地暴露于通过其照射的离子束。 利用该装置，可以执行有效的部分离子注入以补偿晶体管的沟道中的阈值电压Vt的变化，从而提供更均匀的晶体管特性。

公开(公告)号：US20070152267A1

公开(公告)日：2007-07-05

申请号：US11501943

申请日：2006-08-10

申请人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

发明人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/1037 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device having recess gates and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having inverse triangular recesses formed therein; a gate insulating film having a designated thickness formed on the semiconductor substrate; gate electrodes formed on the gate insulating film so that the gate electrodes fill the inverse triangular recesses and protrude from the surface of the semiconductor substrate; and first and second junction regions formed in the semiconductor substrate and opposed to each other so that the corresponding one of the gate electrodes is interposed therebetween.

摘要翻译： 具有凹槽的半导体器件及其制造方法。 半导体器件包括在其中形成有反三角形凹槽的半导体衬底; 在半导体衬底上形成具有指定厚度的栅极绝缘膜; 栅电极形成在栅极绝缘膜上，使得栅电极填充反三角形凹部并从半导体衬底的表面突出; 以及形成在半导体衬底中并且彼此相对的第一和第二接合区域，使得相应的一个栅电极插入其间。

公开(公告)号：US07790551B2

公开(公告)日：2010-09-07

申请号：US12603906

申请日：2009-10-22

申请人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

发明人： Kyoung Bong Rouh ,  Seung Woo Jin ,  Min Yong Lee ,  Yong Soo Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/4236 ,  H01L21/26586 ,  H01L21/28061 ,  H01L29/1041 ,  H01L29/516 ,  H01L29/66621

摘要： A transistor having a recess gate structure and a method for fabricating the same. The transistor includes a gate insulating layer formed on the inner walls of first trenches formed in a semiconductor substrate; a gate conductive layer formed on the gate insulating layer for partially filling the first trenches; gate electrodes formed on the gate conductive layer for completely filling the first trenches, and surrounded by the gate conductive layer; channel regions formed in the semiconductor substrate along the first trenches; and source/drain regions formed in a shallow portion of the semiconductor substrate.

摘要翻译： 具有凹陷栅极结构的晶体管及其制造方法。 晶体管包括形成在形成在半导体衬底中的第一沟槽的内壁上的栅极绝缘层; 形成在所述栅极绝缘层上以部分地填充所述第一沟槽的栅极导电层; 栅极电极，形成在栅极导电层上，用于完全填充第一沟槽，并被栅极导电层包围; 形成在半导体衬底中的第一沟槽区; 以及形成在半导体衬底的浅部中的源极/漏极区域。

公开(公告)号：US20080160730A1

公开(公告)日：2008-07-03

申请号：US11757323

申请日：2007-06-01

申请人： Min Yong LEE ,  Yong Soo JUNG

发明人： Min Yong LEE ,  Yong Soo JUNG

IPC分类号： H01L21/265

CPC分类号： H01L21/26586 ,  H01L29/1045 ,  H01L29/1083

摘要： A method of fabricating a semiconductor device includes forming a mask pattern for exposing a region of a semiconductor substrate. Dopant ions are implanted into the exposed region of the semiconductor substrate at a tilt angle of approximately 4.4° to 7°.

摘要翻译： 制造半导体器件的方法包括形成用于暴露半导体衬底区域的掩模图案。 掺杂离子以约4.4°至7°的倾斜角度注入到半导体衬底的暴露区域中。