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公开(公告)号：US08664707B2
公开(公告)日：2014-03-04
申请号：US13428706
申请日：2012-03-23
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Provided is a semiconductor device that can include a lower interconnection on a substrate and at least one upper interconnection disposed on the lower interconnection. At least one gate structure can be disposed between the upper interconnection and the lower interconnection, where the gate structure can include a plurality of gate lines that are vertically stacked so that each of the gate lines has a wiring portion that is substantially parallel to an upper surface of the substrate and a contact portion that extends from the wiring portion along a direction penetrating an upper surface of the substrate. At least one semiconductor pattern can connect the upper and lower interconnections.
摘要翻译： 提供了一种半导体器件，其可以包括在衬底上的下互连和布置在下互连上的至少一个上互连。 至少一个栅极结构可以设置在上部互连和下部互连之间，其中栅极结构可以包括垂直堆叠的多条栅极线，使得每个栅极线具有基本上平行于上部的布线部分 所述基板的表面和从所述布线部沿着穿过所述基板的上表面的方向延伸的接触部。 至少一个半导体图案可以连接上部和下部互连。
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2.发明申请INTEGRATED CIRCUIT MEMORY DEVICES HAVING VERTICAL TRANSISTOR ARRAYS THEREIN AND METHODS OF FORMING SAME 有权具有垂直晶体管阵列的集成电路存储器件及其形成方法公开(公告)号：US20140015032A1
公开(公告)日：2014-01-16
申请号：US14024737
申请日：2013-09-12
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
摘要翻译： 集成电路器件包括其中具有可独立控制的栅电极的垂直堆叠的晶体管阵列。 提供第一半导体沟道区，其在独立可控栅电极的垂直叠层的第一侧壁上延伸。 还提供了第一电绝缘层，其在第一半导体沟道区域和独立可控栅电极的垂直叠层的第一侧壁之间延伸。 源极和漏极区分别电耦合到第一半导体沟道区的第一和第二端。
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公开(公告)号：US08541832B2
公开(公告)日：2013-09-24
申请号：US12816771
申请日：2010-06-16
IPC分类号： H01L29/792
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
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公开(公告)号：US08164134B2
公开(公告)日：2012-04-24
申请号：US12481403
申请日：2009-06-09
IPC分类号： H01L29/792 , H01L27/108
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.
摘要翻译： 提供半导体器件及其制造方法。 在衬底上形成限定至少一个第一开口的至少一个模具结构，其中模具结构包括顺序地和交替地堆叠的第一模具图案和第二模具图案。 此后，选择性地蚀刻第一模具图案的侧表面以在第二模具图案之间形成底切区域。 然后，形成半导体层以覆盖形成底切区域的模具结构的表面，形成栅极图案，填充形成半导体层的各个底切区域。
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5.发明申请Integrated Circuit Memory Devices Having Vertical Transistor Arrays Therein and Methods of Forming Same 有权具有垂直晶体管阵列的集成电路存储器件及其形成方法相同公开(公告)号：US20110018051A1
公开(公告)日：2011-01-27
申请号：US12816771
申请日：2010-06-16
IPC分类号： H01L27/115
CPC分类号： H01L29/7926 , H01L27/11575 , H01L27/11578 , H01L27/11582 , H01L29/792
摘要： An integrated circuit device includes a transistor array having a vertical stack of independently controllable gate electrodes therein. A first semiconductor channel region is provided, which extends on a first sidewall of the vertical stack of independently controllable gate electrodes. A first electrically insulating layer is also provided, which extends between the first semiconductor channel region and the first sidewall of the vertical stack of independently controllable gate electrodes. Source and drain regions are provided, which are electrically coupled to first and second ends of the first semiconductor channel region, respectively.
摘要翻译： 集成电路器件包括其中具有可独立控制的栅电极的垂直堆叠的晶体管阵列。 提供第一半导体沟道区，其在独立可控栅电极的垂直叠层的第一侧壁上延伸。 还提供了第一电绝缘层，其在第一半导体沟道区域和独立可控栅电极的垂直叠层的第一侧壁之间延伸。 源极和漏极区分别电耦合到第一半导体沟道区的第一和第二端。
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公开(公告)号：US20100308391A1
公开(公告)日：2010-12-09
申请号：US12481403
申请日：2009-06-09
IPC分类号： H01L29/792
CPC分类号： H01L27/11578 , H01L21/8221 , H01L27/0688 , H01L27/11575 , H01L27/11582 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： Provided are a semiconductor device and a method of fabricating the same. At least one mold structure defining at least one first opening is formed on a substrate, wherein the mold structure comprises first mold patterns and second mold patterns that are sequentially and alternatingly stacked. Thereafter, side surfaces of the first mold patterns are selectively etched to form undercut regions between the second mold patterns. Then, a semiconductor layer is formed to cover a surface of the mold structure where the undercut regions are formed, and gate patterns are formed, which fill respective undercut regions where the semiconductor layer is formed.
摘要翻译： 提供半导体器件及其制造方法。 在衬底上形成限定至少一个第一开口的至少一个模具结构，其中模具结构包括顺序地和交替地堆叠的第一模具图案和第二模具图案。 此后，选择性地蚀刻第一模具图案的侧表面以在第二模具图案之间形成底切区域。 然后，形成半导体层以覆盖形成底切区域的模具结构的表面，形成栅极图案，填充形成半导体层的各个底切区域。
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公开(公告)号：US20050064640A1
公开(公告)日：2005-03-24
申请号：US10971353
申请日：2004-10-22
申请人： Yong-jik Park , Ji-Young Kim
发明人： Yong-jik Park , Ji-Young Kim
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06 , H01L29/10
CPC分类号： H01L29/66651 , H01L29/0649 , H01L29/105 , H01L29/66575
摘要： Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an isolation insulating film, an epitaxial silicon layer, a junction blocking insulating film, a gate stack, and source and drain junctions. The isolation insulating film is formed on a semiconductor substrate to define an active area. The epitaxial silicon layer is formed in the active area of the semiconductor substrate and surrounded by the isolation insulating film. The junction blocking insulating film is formed in the epitaxial silicon layer. The gate stack is formed over the epitaxial silicon layer so that the junction blocking insulating film is buried under approximately the center of the gate stack. The source and drain junctions are formed adjacent the sidewalls of the gate stack. Accordingly, a short circuit between source/drain junctions in a bulk area caused by the unwanted diffusion of the junctions can be prevented.
摘要翻译： 提供半导体器件和制造半导体器件的方法。 半导体器件包括隔离绝缘膜，外延硅层，接合阻挡绝缘膜，栅极堆叠以及源极和漏极结。 隔离绝缘膜形成在半导体衬底上以限定有源区。 外延硅层形成在半导体衬底的有源区中并被隔离绝缘膜包围。 接合阻挡绝缘膜形成在外延硅层中。 栅极堆叠形成在外延硅层上，使得接合阻挡绝缘膜被埋在栅堆叠的大约中心附近。 源极和漏极结邻近栅堆叠的侧壁形成。 因此，可以防止由接合点的不想要的扩散引起的在大块区域中的源极/漏极结之间的短路。
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8.发明授权Semiconductor device having an improved packing density and high reliability 失效具有改进的包装密度和高可靠性的半导体装置
公开(公告)号：US5508564A
公开(公告)日：1996-04-16
申请号：US307040
申请日：1994-09-16
申请人： Kyu-pil Lee , Yong-jik Park
发明人： Kyu-pil Lee , Yong-jik Park
IPC分类号： H01L29/78 , H01L21/06 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8249 , H01L23/485 , H01L27/06 , H01L27/088 , H01L27/092 , H01L27/108 , H01L29/40 , H01L29/76 , H01L23/48 , H01L23/52
CPC分类号： H01L23/485 , H01L24/02 , H01L27/10805 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01023 , H01L2924/01033 , H01L2924/01075 , H01L2924/13091 , H01L2924/14
摘要： A semiconductor device is fabricated having contact holes formed in an interlayer insulator and on impurity diffusion regions positioned on either side of an isolator, The contact holes are arranged so as not to be disposed along a shortest line path across the isolator. This arrangement isolating interval and provides a structure which can realize higher packing density and improved reliability.
摘要翻译： 制造了具有形成在层间绝缘体中的接触孔和位于隔离体两侧的杂质扩散区的半导体器件。接触孔布置成不沿隔离器的最短线路布置。 这种布置隔离间隔并提供了可以实现更高包装密度和提高可靠性的结构。
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公开(公告)号：US07091072B2
公开(公告)日：2006-08-15
申请号：US10971353
申请日：2004-10-22
申请人： Yong-jik Park , Ji-Young Kim
发明人： Yong-jik Park , Ji-Young Kim
CPC分类号： H01L29/66651 , H01L29/0649 , H01L29/105 , H01L29/66575
摘要： Provided are a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes an isolation insulating film, an epitaxial silicon layer, a junction blocking insulating film, a gate stack, and source and drain junctions. The isolation insulating film is formed on a semiconductor substrate to define an active area. The epitaxial silicon layer is formed in the active area of the semiconductor substrate and surrounded by the isolation insulating film. The junction blocking insulating film is formed in the epitaxial silicon layer. The gate stack is formed over the epitaxial silicon layer so that the junction blocking insulating film is buried under approximately the center of the gate stack. The source and drain junctions are formed adjacent the sidewalls of the gate stack. Accordingly, a short circuit between source/drain junctions in a bulk area caused by the unwanted diffusion of the junctions can be prevented.
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公开(公告)号：US06248654B1
公开(公告)日：2001-06-19
申请号：US09370880
申请日：1999-08-10
申请人： Joo-Young Lee , Yong Jik Park
发明人： Joo-Young Lee , Yong Jik Park
IPC分类号： H01L2144
CPC分类号： H01L21/76897
摘要： A method of forming a self-aligned contact in a semiconductor device comprising a semiconductor substrate and a gate line. The method comprises the steps of forming a conductive layer on an overall surface of the semiconductor substrate including the gate line, planarization-etching the conductive layer down to the gate line, and etching the conductive layer to form the contact, the etching performed at least until the contact is electrically separated from other portions of the conductive layer. The method may reduce or eliminate pad-to-gate electrode shorts by preventing exposure during etching of the gate electrode, reduce or eliminate pad-to-pad bridging by preventing generation of void regions, and reduce contact resistance by securing enough contact area between a pad and an active region in spite of misalignment of a photoresist pattern.
摘要翻译： 一种在包括半导体衬底和栅极线的半导体器件中形成自对准接触的方法。 该方法包括以下步骤：在包括栅极线的半导体衬底的整个表面上形成导电层，将导电层平坦化蚀刻到栅极线，并蚀刻导电层以形成接触，至少进行蚀刻 直到接触件与导电层的其它部分电分离。 该方法可以通过防止蚀刻栅电极期间的曝光来减少或消除焊盘对栅极电极的短路，通过防止产生空隙区域来减少或消除焊盘到焊盘桥接，并通过确保足够的接触面积来减小接触电阻 衬垫和有源区，尽管光致抗蚀剂图案未对准。
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