公开(公告)号：US20160012879A1

公开(公告)日：2016-01-14

申请号：US14795191

申请日：2015-07-09

申请人： Yoon-Joo EOM ,  JOON-YOUNG PARK ,  YONGCHEOL BAE ,  WON YOUNG LEE ,  SEONGJIN JANG ,  JUNGHWAN CHOI ,  JOOSUN CHOI

发明人： Yoon-Joo EOM ,  JOON-YOUNG PARK ,  YONGCHEOL BAE ,  WON YOUNG LEE ,  SEONGJIN JANG ,  JUNGHWAN CHOI ,  JOOSUN CHOI

IPC分类号： G11C11/4096 ,  G11C11/4093

CPC分类号： G11C11/4096 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/105

摘要： A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

摘要翻译： 公开了一种多通道半导体器件。 多通道器件可以包括衬底，衬底上的第一管芯，并具有用作第一芯片的第一沟道; 以及在所述衬底上的第二管芯，并具有不同于所述第一沟道的第二沟道，用作第二芯片，并且包括与所述第一裸片相同的存储容量和物理尺寸。 内部接口设置在第一和第二管芯之间。 内部接口被配置为传送用于控制第一和第二管芯的内部操作的信息，并且首先将第一和第二管芯的第一接收管芯施加到另一个管芯。

公开(公告)号：US20130182513A1

公开(公告)日：2013-07-18

申请号：US13611867

申请日：2012-09-12

申请人： Yoon-Joo EOM ,  Young-Jin JEON ,  Yong-Cheol BAE ,  Young-Chul CHO

发明人： Yoon-Joo EOM ,  Young-Jin JEON ,  Yong-Cheol BAE ,  Young-Chul CHO

IPC分类号： G11C5/14 ,  H03K19/003 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254 ,  H03K19/0005

摘要： Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

摘要翻译： 提供了一种半导体存储器件和包括该半导体存储器件的存储器系统，其可以考虑到沟道环境和存储器控制器的管芯端接（ODT）电阻的不匹配来校准输出电压的电平。 存储器系统包括存储器控制器和半导体存储器件。 半导体存储器件被配置为基于存储器控制器的驱动信息生成参考电压，并且当半导体存储器件电连接到存储器控制器时，基于参考电压校准输出电压电平。

公开(公告)号：US09105317B2

公开(公告)日：2015-08-11

申请号：US13611867

申请日：2012-09-12

申请人： Yoon-Joo Eom ,  Young-Jin Jeon ,  Yong-Cheol Bae ,  Young-Chul Cho

发明人： Yoon-Joo Eom ,  Young-Jin Jeon ,  Yong-Cheol Bae ,  Young-Chul Cho

IPC分类号： H03K19/003 ,  G11C7/10 ,  H03K19/00 ,  G11C29/02

CPC分类号： G11C7/1057 ,  G11C29/021 ,  G11C29/028 ,  G11C2207/2254 ,  H03K19/0005

摘要： Provided are a semiconductor memory device and a memory system including the same, which may calibrate a level of an output voltage in consideration of channel environment and a mismatch in on-die termination (ODT) resistance of a memory controller. The memory system includes a memory controller and a semiconductor memory device. The semiconductor memory device is configured to generate a reference voltage based on driving information of the memory controller, and calibrate an output voltage level based on a reference voltage when the semiconductor memory device is electrically connected to the memory controller.

摘要翻译： 提供了一种半导体存储器件和包括该半导体存储器件的存储器系统，其可以考虑到沟道环境和存储器控制器的管芯端接（ODT）电阻的不匹配来校准输出电压的电平。 存储器系统包括存储器控制器和半导体存储器件。 半导体存储器件被配置为基于存储器控制器的驱动信息生成参考电压，并且当半导体存储器件电连接到存储器控制器时，基于参考电压校准输出电压电平。