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    On-die termination circuit, memory device, memory module, and method of operating and training an on-die termination
    2.
    发明授权
    On-die termination circuit, memory device, memory module, and method of operating and training an on-die termination 有权
    片上终端电路，存储器件，存储器模块以及对片上端接操作和训练的方法

    公开(公告)号：US08619492B2

    公开(公告)日：2013-12-31

    申请号：US12917566

    申请日：2010-11-02

    申请人： Young-Jin Jeon

    发明人： Young-Jin Jeon

    IPC分类号： G11C8/00

    CPC分类号： G11C7/1057 ,  G11C7/1084 ,  G11C7/109 ,  G11C7/222

    摘要： An on-die termination (ODT) circuit of a memory device comprising: a memory device having a memory core having a memory cell array; a data input/output pin connected to the memory core through a data buffer; and an on-die termination (ODT) circuit, comprising: a termination circuit configured to provide a termination impedance at the input/output data pin, the termination circuit having a switching device that selectively connects a termination impedance to the input/output data pin based on the presence of an asynchronous control signal (ACS), wherein the ACS is generated based on the presence of a memory WRITE command. The memory device may further comprise a training circuit comprising: an asynchronous signal delay configured to delay the signal path of the ACS signal to the termination circuit; and a comparing unit configured to compare a phase difference between the ACS signal and a reference signal, the comparing unit comprising a phase detector and a replica delay, wherein the replica delay is configured to delay the signal path of the ACS signal to the phase detector, and the phase detector is configured to output the phase difference as training result.

    摘要翻译： 一种存储器件的片上终端（ODT）电路，包括：具有存储器芯的存储器件，所述存储器芯具有存储单元阵列; 数据输入/输出引脚，通过数据缓冲器连接到存储器核心; 和芯片上终端（ODT）电路，包括：终端电路，被配置为在所述输入/输出数据引脚处提供终端阻抗，所述终端电路具有选择性地将终端阻抗连接到所述输入/输出数据引脚 基于异步控制信号（ACS）的存在，其中基于存储器写入命令的存在来生成ACS。 存储器件还可以包括训练电路，包括：异步信号延迟，被配置为将ACS信号的信号路径延迟到终端电路; 以及比较单元，被配置为比较所述ACS信号和参考信号之间的相位差，所述比较单元包括相位检测器和复制延迟，其中所述复制延迟被配置为将所述ACS信号的信号路径延迟到所述相位检测器 并且相位检测器被配置为输出相位差作为训练结果。

    DATA RECEIVING APPARATUS USING SEMI-DUAL REFERENCE VOLTAGE
    3.
    发明申请
    DATA RECEIVING APPARATUS USING SEMI-DUAL REFERENCE VOLTAGE 有权
    使用双参考电压的数据接收装置

    公开(公告)号：US20080042690A1

    公开(公告)日：2008-02-21

    申请号：US11747685

    申请日：2007-05-11

    申请人： Yang-ki Kim ,  Young-jin Jeon

    发明人： Yang-ki Kim ,  Young-jin Jeon

    IPC分类号： G01R25/00

    CPC分类号： H04L25/0292

    摘要： A semi-dual reference voltage data receiving apparatus includes a first input buffer, a second input buffer, and a phase detector wherein the first input buffer includes a first input receiving unit, a first sense amplifier, and a first current offset controlling unit. The first sense amplifier senses and amplifies the voltage difference between the voltage of a first terminal of a first input transistor and the voltage of a first terminal of a second input transistor. The first current offset controlling unit controls the offset of the current that flows through the second terminal of the second input transistor.

    摘要翻译： 半双参考电压数据接收装置包括第一输入缓冲器，第二输入缓冲器和相位检测器，其中第一输入缓冲器包括第一输入接收单元，第一读出放大器和第一电流偏移控制单元。 第一读出放大器感测并放大第一输入晶体管的第一端子的电压与第二输入晶体管的第一端子的电压之间的电压差。 第一电流偏移控制单元控制流过第二输入晶体管的第二端子的电流的偏移。

    SERIALIZER AND METHOD OF CONVERTING PARALLEL DATA INTO SERIAL DATA
    4.
    发明申请
    SERIALIZER AND METHOD OF CONVERTING PARALLEL DATA INTO SERIAL DATA 有权
    将并行数据转换为串行数据的串行数据和方法

    公开(公告)号：US20070194956A1

    公开(公告)日：2007-08-23

    申请号：US11677021

    申请日：2007-02-20

    申请人： Young-Jin JEON

    发明人： Young-Jin JEON

    IPC分类号： H03M9/00

    CPC分类号： H03M9/00

    摘要： A serializer including a pull-up unit configured to pull up an output node, and a plurality of data select units configured to receive a plurality of input data signals. Each data select unit includes a pull-up device configured to pull up the output node in response to a corresponding input data signal, and a pull-down device configured to pull down the output node in response to the corresponding input data signal.

    摘要翻译： 包括被配置为上拉输出节点的上拉单元的串行器以及被配置为接收多个输入数据信号的多个数据选择单元。 每个数据选择单元包括被配置为响应于相应的输入数据信号来上拉输出节点的上拉装置，以及配置成响应于相应的输入数据信号来下拉输出节点的下拉装置。

    Dual reference input receiver of semiconductor device and method of receiving input data signal
    5.
    发明申请
    Dual reference input receiver of semiconductor device and method of receiving input data signal 有权
    半导体器件的双参考输入接收器和接收输入数据信号的方法

    公开(公告)号：US20070064504A1

    公开(公告)日：2007-03-22

    申请号：US11501073

    申请日：2006-08-09

    申请人： Young-jin Jeon

    发明人： Young-jin Jeon

    IPC分类号： G11C7/10

    CPC分类号： H04L25/061 ,  H04L25/0292

    摘要： A dual reference input receiver, and a method of receiving, wherein the input receiver includes a first input buffer which is synchronized with and enabled by a clock signal, senses a difference between the input data signal and a first reference voltage, and amplifies the sensing result; a second input buffer which is synchronized with and enabled by the clock signal, senses a difference between a second reference voltage and the input data signal, and amplifies the sensing result; and a phase detector which detects a difference between a phase of output signals of the first and second input buffers, and outputs a signal corresponding to the detection result. The first and second reference voltages may respectively be higher and lower than a median voltage of the input data signal. Thus, a single input data signal is advantageously used and a wide input data eye is provided.

    摘要翻译： 一种双参考输入接收机和一种接收方法，其中输入接收机包括与时钟信号同步并由时钟信号使能的第一输入缓冲器，感测输入数据信号和第一参考电压之间的差异，并放大感测 结果; 与时钟信号同步并使能的第二输入缓冲器感测第二参考电压和输入数据信号之间的差异，并放大感测结果; 以及相位检测器，其检测第一和第二输入缓冲器的输出信号的相位差，并输出与检测结果相对应的信号。 第一和第二参考电压可以分别高于和低于输入数据信号的中值电压。 因此，有利地使用单个输入数据信号，并提供宽输入数据眼睛。

    Clock divider and method for dividing a clock signal in a DLL circuit
    7.
    发明授权
    Clock divider and method for dividing a clock signal in a DLL circuit 有权
    用于对DLL电路中的时钟信号进行分频的时钟分频器和方法

    公开(公告)号：US06815985B2

    公开(公告)日：2004-11-09

    申请号：US10331268

    申请日：2002-12-30

    申请人： Young-Jin Jeon

    发明人： Young-Jin Jeon

    IPC分类号： H03K2100

    CPC分类号： H03K21/10

    摘要： A clock divider in a DLL circuit for generating an internal clock signal synchronized with an external clock signal includes; a first clock dividing circuit for generating a first signal clock by dividing an input clock signal having a same period as a period of the external clock signal, a second clock dividing circuit for generating both a second clock signal and a third clock signal by dividing the first clock signal, a selection signal generation circuit for generating a selection signal in response to plurality of control signals, and a clock signal selection circuit for selectively outputting the second clock signal or the third clock signal in response to the selection signal.

    摘要翻译： 用于产生与外部时钟信号同步的内部时钟信号的DLL电路中的时钟分频器包括： 第一时钟分频电路，用于通过将与外部时钟信号的周期相同的周期的输入时钟信号除以来产生第一信号时钟;第二时钟分频电路，用于通过将第二时钟信号和第三时钟信号除以第二时钟信号和第三时钟信号 第一时钟信号，响应于多个控制信号产生选择信号的选择信号产生电路，以及响应于选择信号有选择地输出第二时钟信号或第三时钟信号的时钟信号选择电路。

    Power mixing circuit and semiconductor memory device including the same
    9.
    发明授权
    Power mixing circuit and semiconductor memory device including the same 有权
    功率混合电路和包括其的半导体存储器件

    公开(公告)号：US09076510B2

    公开(公告)日：2015-07-07

    申请号：US13619793

    申请日：2012-09-14

    申请人： Young-Chul Cho ,  Young-Jin Jeon ,  Yong-Cheol Bae

    发明人： Young-Chul Cho ,  Young-Jin Jeon ,  Yong-Cheol Bae

    IPC分类号： G11C5/14 ,  G11C7/02 ,  G11C7/10 ,  G11C7/20 ,  G11C5/04

    CPC分类号： G11C5/147 ,  G11C5/04 ,  G11C5/148 ,  G11C7/02 ,  G11C7/1012 ,  G11C7/1057 ,  G11C7/20

    摘要： A power mixing circuit capable of maintaining a stable output voltage in a deep-power-down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.

    摘要翻译： 提供了能够在深度掉电模式下保持稳定的输出电压的功率混合电路。 功率混合电路包括输入缓冲器，功率混合控制电路，功率混合驱动器和输出缓冲器。 输入缓冲器被配置为使用第一电源电压进行操作，并且响应于输入信号产生第一电压信号。 功率混合控制电路被配置为基于上电信号和深度掉电模式信号来产生功率混合控制信号。 功率混合驱动器被配置为使用外部电源电压和第二电源电压进行操作，以对外部电源电压和第二电源电压进行功率混合，并产生第二电压信号。 输出缓冲器被配置为使用第二电源电压进行操作，并且产生输出信号。