公开(公告)号：US20130200922A1

公开(公告)日：2013-08-08

申请号：US13548079

申请日：2012-07-12

Applicant: Yu-Li HSUEH ,  Jing-Hong Conan ZHAN

Inventor： Yu-Li HSUEH ,  Jing-Hong Conan ZHAN

IPC: H03L7/089

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/1072

Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.

Abstract translation: 本发明提供了一种解决方案，通过各种电路配置通过各种电路配置升级相位频率检测器（PFD）和电荷泵（CP）增益，提供令人满意的性能，而不需要锁相环（PLL）电路的显着占地面积， 采用一个或多个触发器，延迟元件和高级电路技术。

公开(公告)号：US08319532B2

公开(公告)日：2012-11-27

申请号：US13097050

申请日：2011-04-28

Applicant: Yu-Li Hsueh ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Jing-Hong Conan Zhan

IPC: H03K21/00

CPC classification number: H03L7/18 ,  H03K21/026

Abstract: A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.

Abstract translation: 分频器包括相位选择器和定时电路。 相位选择器被布置成根据控制信号接收多个输入信号和多个控制信号并输出​​多个输出信号，其中选择性地选择预定参考电压和输入信号以根据 控制信号和输入信号具有相同的频率但不同的相位。 定时电路被配置为接收输出信号并根据输出信号产生控制信号。

公开(公告)号：US07612625B2

公开(公告)日：2009-11-03

申请号：US12070440

申请日：2008-02-19

Applicant: Miaobin Gao ,  Yu-Li Hsueh ,  Chien-Chang Liu

Inventor： Miaobin Gao ,  Yu-Li Hsueh ,  Chien-Chang Liu

IPC: H03B5/12 ,  H03B27/00 ,  H03L7/099

CPC classification number: H03L7/0891 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1271 ,  H03B5/1293 ,  H03L7/089 ,  H03L7/099

Abstract: In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有压控振荡器（VCO）的装置，用于产生具有由第一和第二偏置电流的偏置电流耦合比率控制的频率的第一时钟信号，以及耦合到VCO的控制电路 产生第一对控制信号以调整偏置电流耦合比。 描述和要求保护其他实施例。

公开(公告)号：US08461933B2

公开(公告)日：2013-06-11

申请号：US13070425

申请日：2011-03-23

Applicant: Yi-Hsien Cho ,  Yu-Li Hsueh

Inventor： Yi-Hsien Cho ,  Yu-Li Hsueh

IPC: H03L7/08 ,  H03L7/18

CPC classification number: H03L7/099 ,  H03L7/181 ,  H03L7/193 ,  H03L2207/06

Abstract: The frequency calibration device includes a logic unit for gating the clock signal according to a gating window signal to generate a gated clock signal, and a divider for dividing the gated clock signal by a divisor in frequency to generate a frequency indication signal, and output digits of the divider are set to the divisor in a calibration cycle, and the frequency indication signal is a most significant bit of the output digits.

Abstract translation: 频率校准装置包括用于根据选通窗口信号门控时钟信号以产生门控时钟信号的逻辑单元，以及用于将门控时钟信号除以频率除数以产生频率指示信号的分频器，并输出数字 的分频器在校准周期中设置为除数，频率指示信号是输出数字的最高有效位。

公开(公告)号：US20120133404A1

公开(公告)日：2012-05-31

申请号：US13095873

申请日：2011-04-28

Applicant: Yu-Li Hsueh ,  Yi-Hsien Cho ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Yi-Hsien Cho ,  Jing-Hong Conan Zhan

IPC: H03L7/06

CPC classification number: H03L5/00 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/093

Abstract: A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.

Abstract translation: 电荷泵设置在相位锁定系统中。 电荷泵包括源元件，排液元件和偏移元件。 源极元件被布置成根据第一控制信号选择性地将第一电流源流到电荷泵的输出端，并且排水元件被布置成根据第二控制信号从输出端选择性地排出第二电流。 偏移元件布置成根据第三控制信号经由输出端选择性地导通偏移电流，并且当锁相系统处于锁相状态时，源元件和排液元件之一被禁用。

公开(公告)号：US20090208226A1

公开(公告)日：2009-08-20

申请号：US12070440

申请日：2008-02-19

Applicant: Miaobin Gao ,  Yu-Li Hsueh ,  Chien-Chang Liu

Inventor： Miaobin Gao ,  Yu-Li Hsueh ,  Chien-Chang Liu

IPC: H04B10/06 ,  H03L7/087

CPC classification number: H03L7/0891 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1271 ,  H03B5/1293 ,  H03L7/089 ,  H03L7/099

Abstract: In one embodiment, the present invention includes an apparatus having a voltage controlled oscillator (VCO) to generate a first clock signal having a frequency controlled by a bias current coupling ratio of first and second bias currents, and a control circuit coupled to the VCO to generate a first pair of control signals to adjust the bias current coupling ratio. Other embodiments are described and claimed.

公开(公告)号：US20090074123A1

公开(公告)日：2009-03-19

申请号：US11855857

申请日：2007-09-14

Applicant: Yu-Li Hsueh ,  Miaobin Gao ,  Chien-Chang Liu

Inventor： Yu-Li Hsueh ,  Miaobin Gao ,  Chien-Chang Liu

IPC: H04L7/02

CPC classification number: H04L7/033 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/091 ,  H03L7/113

Abstract: A stream of data may flow over a fiber or other medium without any accompanying clock signal. The receiving device may then be required to process this data synchronously. Embodiments describe clock and data recovery (CDR) circuits which may sample a data signal at a plurality of sampling points to partition a clock cycle into four phase regions P1, P2, P3, and P4 which may be represented on a phase plane being divided into four quadrants. A relative phase between a data signal transition edge and a clock phase may be represented by a phasor on the phase plane. The clock phase and frequency may be adjusted by determining the instantaneous location of the phasor and the direction of phasor rotation in the phase plane.

Abstract translation: 数据流可以在光纤或其他介质上流动，而没有任何伴随的时钟信号。 然后可能需要接收设备同步处理该数据。 实施例描述了时钟和数据恢复（CDR）电路，其可以在多个采样点处对数据信号进行采样，以将时钟周期划分成四个相位区域P1，P2，P3和P4，这四个相位区域P1，P2，P3和P4可分为 四象限。 数据信号转换边沿和时钟相位之间的相对相位可以由相位平面上的相量表示。 可以通过确定相量的瞬时位置和相平面中相量旋转的方向来调节时钟相位和频率。

公开(公告)号：US08664985B2

公开(公告)日：2014-03-04

申请号：US13548079

申请日：2012-07-12

Applicant: Yu-Li Hsueh ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Jing-Hong Conan Zhan

IPC: H03L7/06

CPC classification number: H03L7/10 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/1072

Abstract: The present invention provides for a solution to reduce locking time with satisfactory performance without the need for significant footprint area for the phase lock loop (PLL) circuits by boosting phase frequency detector (PFD) and charge pump (CP) gains through various circuitry configurations that employ one or more flip-flops, delay elements and advanced circuitry techniques.

Abstract translation: 本发明提供了一种解决方案，通过各种电路配置通过各种电路配置升级相位频率检测器（PFD）和电荷泵（CP）增益，提供令人满意的性能，而不需要锁相环（PLL）电路的显着占地面积， 采用一个或多个触发器，延迟元件和高级电路技术。

公开(公告)号：US08400199B2

公开(公告)日：2013-03-19

申请号：US13095873

申请日：2011-04-28

Applicant: Yu-Li Hsueh ,  Yi-Hsien Cho ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Yi-Hsien Cho ,  Jing-Hong Conan Zhan

IPC: H03L7/06

CPC classification number: H03L5/00 ,  H03L7/089 ,  H03L7/0895 ,  H03L7/0896 ,  H03L7/093

Abstract: A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.

Abstract translation: 电荷泵设置在相位锁定系统中。 电荷泵包括源元件，排液元件和偏移元件。 源极元件被布置成根据第一控制信号选择性地将第一电流源流到电荷泵的输出端，并且排水元件被布置成根据第二控制信号从输出端选择性地排出第二电流。 偏移元件布置成根据第三控制信号经由输出端选择性地导通偏移电流，并且当锁相系统处于锁相状态时，源元件和排液元件之一被禁用。

公开(公告)号：US20120126862A1

公开(公告)日：2012-05-24

申请号：US13097050

申请日：2011-04-28

Applicant: Yu-Li Hsueh ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Jing-Hong Conan Zhan

IPC: H03K21/00

CPC classification number: H03L7/18 ,  H03K21/026

Abstract: A frequency divider comprises a phase selector and a timing circuit. The phase selector is arranged to receive a plurality of input signals and a plurality of control signals and output a plurality of output signals according to the control signals, wherein a predetermined reference voltage and the input signals are selectively chosen to generate the output signals according to the control signals, and the input signals are of a same frequency but different phases. The timing circuit is arranged to receive the output signals and generate the control signals according to the output signals.

Abstract translation: 分频器包括相位选择器和定时电路。 相位选择器被布置成根据控制信号接收多个输入信号和多个控制信号并输出​​多个输出信号，其中选择性地选择预定参考电压和输入信号以根据 控制信号和输入信号具有相同的频率但不同的相位。 定时电路被配置为接收输出信号并根据输出信号产生控制信号。