公开(公告)号：US08653564B1

公开(公告)日：2014-02-18

申请号：US12551581

申请日：2009-09-01

Applicant: Jing-Hong Conan Zhan

Inventor： Jing-Hong Conan Zhan

IPC: H01L29/76

CPC classification number: H01L29/78 ,  H01L27/0207 ,  H01L29/4238

Abstract: A millimeter-wave transistor device includes a plurality of sub-cells arranged in matrix array, each of the sub-cells having a longitudinal gate finger elongating along a reference y-axis, a source doping region disposed at one side of the longitudinal gate finger and a drain doping region at the other side of the longitudinal gate finger opposite to the source doping region; and at least three parallel connecting bars extending along a reference x-axis, electrically connecting with respective distal ends of the longitudinal gate finger of each of the sub-cells.

Abstract translation: 毫米波晶体管器件包括以矩阵阵列排列的多个子单元，每个子单元具有沿着参考y轴延伸的纵向栅极指状，源极掺杂区域设置在纵向栅极指状物的一侧 以及在所述纵向栅极指与所述源极掺杂区域相对的另一侧的漏极掺杂区域; 以及沿着参考x轴延伸的至少三个平行连接杆，与每个子单元的纵向门指的相应远端电连接。

公开(公告)号：US20130141149A1

公开(公告)日：2013-06-06

申请号：US13612729

申请日：2012-09-12

Applicant: Yu-Li HSUEH ,  Chih-Hsien SHEN ,  Jing-Hong Conan ZHAN

Inventor： Yu-Li HSUEH ,  Chih-Hsien SHEN ,  Jing-Hong Conan ZHAN

IPC: H03K3/017

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.

Abstract translation: 用于占空比校准的装置包括输入校准电路，延迟链，第一比较器和第二比较器。 输入校准电路根据第一控制信号校准输入时钟信号，以产生输入校准时钟信号。 延迟链包括串联耦合的多个延迟单元，并延迟输入校准时钟信号，以产生第一延迟时钟信号和第二延迟时钟信号。 延迟单元中的至少两个具有根据第二控制信号来控制的可调延迟时间。 第一比较器将输入校准时钟信号与第一延迟时钟信号进行比较，以产生第一控制信号。 第二比较器将输入校准时钟信号与第二延迟时钟信号进行比较，以产生第二控制信号。

公开(公告)号：US08395453B2

公开(公告)日：2013-03-12

申请号：US12235623

申请日：2008-09-23

Applicant: Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

Inventor： Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

IPC: H03L7/08 ,  H03C3/06

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error or a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.

Abstract translation: 通过预测根据估计的量化误差预测的可能的相位误差来补偿全数字锁相环（ADPLL）内的时间 - 数字转换器（TDC）的相位误差，数字控制 振荡器（DCO），TDC的增益或其组合。 通过适当的导入，可能的相位误差可以由量化误差进一步指示，对应于具有TDC的TDC模块接收的参考周期的一半的代码方差，ADPLL的分频器的分频比，分数 与量化误差相关的数字或其组合。 数字相位误差消除模块还用于产生用于补偿TDC的相位误差的可能的相位误差。

公开(公告)号：US20130005275A1

公开(公告)日：2013-01-03

申请号：US13301002

申请日：2011-11-21

Applicant: Sean Timothy Nicolson ,  Jing-Hong Conan Zhan

Inventor： Sean Timothy Nicolson ,  Jing-Hong Conan Zhan

IPC: H04B1/40

CPC classification number: H04B1/48

Abstract: The transceiver has a transmitter, a receiver, and a three-port network. The transmitter is configured to transmit an outgoing RF signal. The receiver is configured to receive an incoming RF signal. The three-port network includes: a transmission line, configured to have a line length less than a quarter of a wavelength of the incoming RF signal; an antenna port, configured to connect to an antenna; a receiver port, configured to connect the receiver to the antenna port; and a transmitter port, configured to connect the transmitter to the antenna port and the receiver port through the transmission line.

Abstract translation: 收发器具有发射器，接收器和三端口网络。 发射器被配置为发送输出RF信号。 接收器被配置为接收输入的RF信号。 三端口网络包括：传输线，其被配置为具有小于输入RF信号的波长的四分之一的线路长度; 天线端口，被配置为连接到天线; 接收器端口，被配置为将接收器连接到天线端口; 以及发射器端口，被配置为通过传输线将发射器连接到天线端口和接收器端口。

公开(公告)号：US08228128B2

公开(公告)日：2012-07-24

申请号：US12838502

申请日：2010-07-19

Applicant: Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

Inventor： Hsiang-Hui Chang ,  Ping-Ying Wang ,  Jing-Hong Conan Zhan ,  Bing-Yu Hsieh

IPC: H03L7/085

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract translation: 为了减少模拟锁相环中的误差，使用具有数字组件和数字操作的全数字锁相环（ADPLL）。 ADPLL也可用于直接调频（DFM）。 通过将ADPLL的比例路径增益定义为ADPLL的带宽和参考频率，通过TDC增益，DCO增益，分频器的分频比，放大器的增益或其组合，增益 可以调整放大器，使得可以良好校准ADPLL的最佳环路带宽。 为了达到ADPLL完全数字化的目的，TDC和DCO的收益可能会以数字方式进一步调整。

公开(公告)号：US07728686B2

公开(公告)日：2010-06-01

申请号：US12235606

申请日：2008-09-23

Applicant: Jing-Hong Conan Zhan ,  Ping-Ying Wang ,  Hsiang-Hui Chang

Inventor： Jing-Hong Conan Zhan ,  Ping-Ying Wang ,  Hsiang-Hui Chang

IPC: H03B5/12 ,  H03B5/18 ,  H03L7/085 ,  H03L7/099

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: A digital-controlled oscillator (DCO) is utilized in an all-digital phase-locked loop for eliminating frequency discontinuities. The DCO includes a tank module and a negative gm cell. The tank module comprises a plurality of cells, at least a portion of the cells comprising a first tracking set and a second tracking set for respectively handling an odd bit or an even bit. The odd bit and the even bit are related to an integer signal, a fractional signal or a combination thereof, the fractional signal is indicated by a primary voltage inputted to the DCO. With the DCO, frequency discontinuities and undesired spurs are eliminated.

Abstract translation: 数字控制振荡器（DCO）用于全数字锁相环，用于消除频率不连续性。 DCO包括罐模块和负gm单元。 所述箱模块包括多个单元，所述单元的至少一部分包括用于分别处理奇数位或偶位的第一跟踪集和第二跟踪集。 奇数位和偶位与整数信号，分数信号或其组合相关，分数信号由输入到DCO的初级电压表示。 使用DCO，消除了频率不连续性和不期望的刺激。

公开(公告)号：US09088448B2

公开(公告)日：2015-07-21

申请号：US13612811

申请日：2012-09-12

Applicant: Sean Timothy Nicolson ,  ChuanKang Liang ,  Jing-Hong Conan Zhan

Inventor： Sean Timothy Nicolson ,  ChuanKang Liang ,  Jing-Hong Conan Zhan

IPC: H03H7/30 ,  H04L25/03 ,  H01Q3/26

CPC classification number: H04B17/14 ,  H01Q3/267 ,  H04B7/04 ,  H04L25/03878

Abstract: The calibration method, performed on a phased array device including channel elements coupled in parallel by a transmission line, has the steps of: obtaining channel responses corresponding to the channel elements through the transmission line, and each of the channel responses is obtained when one of the channel elements is turned on, and the rest of the channel elements are turned off; calculating a characteristic value corresponding to the transmission line based on the obtained channel responses of the channel elements; and adjusting a channel parameter of one of the channel elements based on the characteristic value of the transmission line.

Abstract translation: 在包括通过传输线并联耦合的信道单元的相控阵器件上执行的校准方法具有以下步骤：通过传输线获得对应于信道单元的信道响应，并且当以下之一获得每个信道响应时 通道元件接通，其余通道元件关闭; 基于所获得的信道要素的信道响应，计算与所述传输线对应的特征值; 以及基于所述传输线的特征值来调整所述信道单元之一的信道参数。

公开(公告)号：US08878582B2

公开(公告)日：2014-11-04

申请号：US13612729

申请日：2012-09-12

Applicant: Yu-Li Hsueh ,  Chih-Hsien Shen ,  Jing-Hong Conan Zhan

Inventor： Yu-Li Hsueh ,  Chih-Hsien Shen ,  Jing-Hong Conan Zhan

IPC: H03K3/017 ,  H03K5/156

CPC classification number: H03K3/017 ,  H03K5/1565

Abstract: An apparatus for duty cycle calibration includes an input calibration circuit, a delay chain, a first comparator, and a second comparator. The input calibration circuit calibrates an input clock signal according to a first control signal so as to generate an input calibration clock signal. The delay chain includes a plurality of delay units coupled in series, and delays the input calibration clock signal so as to generate a first delay clock signal and a second delay clock signal. At least two of the delay units each have an adjustable delay time which is controlled according to a second control signal. The first comparator compares the input calibration clock signal with the first delay clock signal so as to generate the first control signal. The second comparator compares the input calibration clock signal with the second delay clock signal so as to generate the second control signal.

Abstract translation: 用于占空比校准的装置包括输入校准电路，延迟链，第一比较器和第二比较器。 输入校准电路根据第一控制信号校准输入时钟信号，以产生输入校准时钟信号。 延迟链包括串联耦合的多个延迟单元，并延迟输入校准时钟信号，以产生第一延迟时钟信号和第二延迟时钟信号。 延迟单元中的至少两个具有根据第二控制信号来控制的可调延迟时间。 第一比较器将输入校准时钟信号与第一延迟时钟信号进行比较，以产生第一控制信号。 第二比较器将输入校准时钟信号与第二延迟时钟信号进行比较，以产生第二控制信号。

公开(公告)号：US08429487B2

公开(公告)日：2013-04-23

申请号：US12982918

申请日：2010-12-31

Applicant: Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

Inventor： Hsiang-Hui Chang ,  Bing-Yu Hsieh ,  Jing-Hong Conan Zhan

IPC: H03M13/00

CPC classification number: H03L7/085 ,  H03L7/0991 ,  H03L2207/50

Abstract: An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.

Abstract translation: 用于全数字锁相环（ADPLL）的时间 - 数字转换器（TDC）解码器的误差保护方法包括：检索由TDC解码器接收的数字码; 检索由TDC解码器接收的周期代码; 对数字代码的第一预定位执行异或运算，以及循环码的第二预定位用于产生错误保护代码; 并且通过将错误保护代码添加到周期代码中并将循环码移位第三预定位数，并使用错误保护代码来修正周期代码内的错误。

公开(公告)号：US20120294338A1

公开(公告)日：2012-11-22

申请号：US13301811

申请日：2011-11-22

Applicant: Jing-Hong Conan Zhan ,  Chuan-Kang Liang ,  Ti-Ku Yu ,  Zhiming Deng

Inventor： Jing-Hong Conan Zhan ,  Chuan-Kang Liang ,  Ti-Ku Yu ,  Zhiming Deng

IPC: H04B1/38

CPC classification number: H04B1/40 ,  H01Q3/30 ,  H01Q21/0025 ,  H03F3/19 ,  H03F3/21 ,  H03F2200/294 ,  H03F2200/451 ,  H04B1/44

Abstract: A phased-array transceiver includes: a plurality of antennas; a plurality of transceiving elements respectively coupled to the plurality of antennas, at least one of the transceiving elements comprising a first transmitting circuit and a first receiving circuit; a signal processing block; and a first distributed network, coupled between the signal processing block and the transceiving elements, wherein the transceiving elements, the signal processing block, and the first distributed network are configured as a single chip, and a first path from the antenna through the first receiving circuit to the signal processing block and a second path from the signal processing block through the first transmitting circuit to the antenna share at least partial signal traces of the phased-array transceiver.

Abstract translation: 相控阵收发器包括：多个天线; 分别耦合到所述多个天线的多个收发元件，所述收发元件中的至少一个包括第一发送电路和第一接收电路; 信号处理块; 以及耦合在所述信号处理块和所述收发元件之间的第一分布式网络，其中所述收发元件，所述信号处理块和所述第一分布式网络被配置为单个芯片，以及从所述天线通过所述第一接收的第一路径 信号处理块的电路和从信号处理块通过第一发送电路到天线的第二路径共享相控阵收发器的至少部分信号迹线。