公开(公告)号：US10303480B2

公开(公告)日：2019-05-28

申请号：US14067564

申请日：2013-10-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A Kaplan ,  Daniel Hopper ,  John M. King ,  Jeff Rupley

IPC: G06F9/38 ,  G06F12/0875

Abstract: Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.

公开(公告)号：US20140189245A1

公开(公告)日：2014-07-03

申请号：US13731292

申请日：2012-12-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jeff Rupley ,  Tarun Nakra

IPC: G06F12/12

CPC classification number: G06F12/0811 ,  G06F5/065 ,  G06F12/0808 ,  G06F13/1673

Abstract: A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.

Abstract translation: 在一些实施例中，处理器包括第一高速缓冲存储器和总线单元。 总线单元包括多个缓冲器，并且可操作以分配用于与要存储在第一高速缓冲存储器中的第一高速缓存行相关联的填充请求的多个缓冲器的选定缓冲器，将填充数据从第一高速缓存行加载到 并且将填充数据与从所选择的缓冲器中的第一高速缓冲存储器中取出的驱逐规则数据并行地传送到第一缓存存储器。

公开(公告)号：US20150121010A1

公开(公告)日：2015-04-30

申请号：US14067564

申请日：2013-10-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A Kaplan ,  Daniel Hopper ,  John M. King ,  Jeff Rupley

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F12/0875 ,  G06F9/3826 ,  G06F9/3834 ,  Y02D10/13

Abstract: Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.

Abstract translation: 这里的实施例提供了改进的存储到负载转发（STLF）逻辑和线性混叠效应降低逻辑。 在一个实施例中，选择要执行的加载指令。 确定与所述加载指令相关联的第一线性地址是否与队列中的多个存储指令的存储指令的线性地址匹配。 响应于确定第一线性地址与存储指令的线性地址匹配，转发与用于执行所述加载指令的所述存储指令相关联的数据。

公开(公告)号：US20140310500A1

公开(公告)日：2014-10-16

申请号：US13861267

申请日：2013-04-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. Kaplan ,  Jeff Rupley

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F9/30043 ,  G06F9/3824

Abstract: The present application describes embodiments of a method and apparatus including a page cross misalign buffer. Some embodiments of the apparatus include a store queue for a plurality of entries configured to store information associated with store instructions. A respective entry in the store queue can store a first portion of information associated with a page crossing store instruction. Some embodiments of the apparatus also include one or more buffers configured to store a second portion of information associated with the page crossing store instruction.

Abstract translation: 本申请描述了包括页面交叉对准缓冲器的方法和装置的实施例。 该装置的一些实施例包括用于多个条目的存储队列，其被配置为存储与存储指令相关联的信息。 存储队列中的相应条目可以存储与页面交叉存储指令相关联的信息的第一部分。 该装置的一些实施例还包括配置成存储与页面交叉存储指令相关联的信息的第二部分的一个或多个缓冲器。

公开(公告)号：US20140129776A1

公开(公告)日：2014-05-08

申请号：US13667095

申请日：2012-11-02

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A. Kaplan ,  Jeff Rupley ,  Tarun Nakra

IPC: G06F12/08

CPC classification number: G06F9/30065 ,  G06F9/30043 ,  G06F9/3861 ,  G06F12/0802 ,  G06F12/0815

Abstract: A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.

Abstract translation: 提供了一种用于执行可缓存存储的方法。 该方法包括基于高速缓存行的状态和存储指令的执行阶段确定是否重放存储指令以重新获取一个或多个高速缓存行。 响应于确定重播商店指令而重放存储指令。 提供了一种装置，其包括可配置以基于高速缓存行的状态和存储指令的执行阶段来确定是否重播存储指令以重新获取一个或多个高速缓存行的存储队列（SQ）。 提供了用于使制造设备适应制造装置的计算机可读存储装置。